[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX
From: |
Andrew Jones |
Subject: |
Re: [PATCH v6 1/3] target-arm: Add support for Fujitsu A64FX |
Date: |
Tue, 31 Aug 2021 12:20:02 +0200 |
On Tue, Aug 31, 2021 at 05:29:38PM +0900, Shuuichirou Ishii wrote:
> Add a definition for the Fujitsu A64FX processor.
>
> The A64FX processor does not implement the AArch32 Execution state,
> so there are no associated AArch32 Identification registers.
>
> For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths.
>
> The Identification registers value are defined based on the FX700,
> and have been tested and confirmed.
>
> Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
> ---
> target/arm/cpu64.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
I already gave my r-b on the last posting, but here it is again
Reviewed-by: Andrew Jones <drjones@redhat.com>