Re: [PATCH v6 13/14] target/riscv: Remove RVB (replaced by Zb[abcs]

[Alistair Francis]

On Thu, Aug 26, 2021 at 3:16 AM Philipp Tomsich
<philipp.tomsich@vrull.eu> wrote:
>
> With everything classified as Zb[abcs] and pre-0.93 draft-B
> instructions that are not part of Zb[abcs] removed, we can remove the
> remaining support code for RVB.
>
> Note that RVB has been retired for good and misa.B will neither mean
> 'some' or 'all of' Zb*:
>   https://lists.riscv.org/g/tech-bitmanip/message/532
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Removing RVB moved into a separate commit at the tail-end of the series.
>
>  target/riscv/cpu.c         | 27 ---------------------------
>  target/riscv/cpu.h         |  3 ---
>  target/riscv/insn32.decode |  4 ----
>  3 files changed, 34 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c7bc1f9f44..93bd8f7802 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -127,11 +127,6 @@ static void set_priv_version(CPURISCVState *env, int 
> priv_ver)
>      env->priv_ver = priv_ver;
>  }
>
> -static void set_bext_version(CPURISCVState *env, int bext_ver)
> -{
> -    env->bext_ver = bext_ver;
> -}
> -
>  static void set_vext_version(CPURISCVState *env, int vext_ver)
>  {
>      env->vext_ver = vext_ver;
> @@ -393,7 +388,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>      CPURISCVState *env = &cpu->env;
>      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
>      int priv_version = PRIV_VERSION_1_11_0;
> -    int bext_version = BEXT_VERSION_0_93_0;
>      int vext_version = VEXT_VERSION_0_07_1;
>      target_ulong target_misa = env->misa;
>      Error *local_err = NULL;
> @@ -418,7 +412,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>      }
>
>      set_priv_version(env, priv_version);
> -    set_bext_version(env, bext_version);
>      set_vext_version(env, vext_version);
>
>      if (cpu->cfg.mmu) {
> @@ -496,24 +489,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>          if (cpu->cfg.ext_h) {
>              target_misa |= RVH;
>          }
> -        if (cpu->cfg.ext_b) {
> -            target_misa |= RVB;
> -
> -            if (cpu->cfg.bext_spec) {
> -                if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
> -                    bext_version = BEXT_VERSION_0_93_0;
> -                } else {
> -                    error_setg(errp,
> -                           "Unsupported bitmanip spec version '%s'",
> -                           cpu->cfg.bext_spec);
> -                    return;
> -                }
> -            } else {
> -                qemu_log("bitmanip version is not specified, "
> -                         "use the default value v0.93\n");
> -            }
> -            set_bext_version(env, bext_version);
> -        }
>          if (cpu->cfg.ext_v) {
>              target_misa |= RVV;
>              if (!is_power_of_2(cpu->cfg.vlen)) {
> @@ -584,7 +559,6 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
>      DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
>      /* This is experimental so mark with 'x-' */
> -    DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
>      DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
>      DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
>      DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
> @@ -595,7 +569,6 @@ static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>      DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>      DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> -    DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
>      DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
>      DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
>      DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7c4cd8ea89..77e8b06106 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -67,7 +67,6 @@
>  #define RVS RV('S')
>  #define RVU RV('U')
>  #define RVH RV('H')
> -#define RVB RV('B')
>
>  /* S extension denotes that Supervisor mode exists, however it is possible
>     to have a core that support S mode but does not have an MMU and there
> @@ -83,7 +82,6 @@ enum {
>  #define PRIV_VERSION_1_10_0 0x00011000
>  #define PRIV_VERSION_1_11_0 0x00011100
>
> -#define BEXT_VERSION_0_93_0 0x00009300
>  #define VEXT_VERSION_0_07_1 0x00000701
>
>  enum {
> @@ -288,7 +286,6 @@ struct RISCVCPU {
>          bool ext_f;
>          bool ext_d;
>          bool ext_c;
> -        bool ext_b;
>          bool ext_s;
>          bool ext_u;
>          bool ext_h;
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index abf794095a..0f6020ccb1 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -711,10 +711,6 @@ rorw       0110000 .......... 101 ..... 0111011 @r
>  # instruction, so we use different handler functions to differentiate.
>  zext_h_64  0000100 00000 ..... 100 ..... 0111011 @r2
>
> -# *** RV32B Standard Extension ***
> -
> -# *** RV64B Standard Extension (in addition to RV32B) ***
> -
>  # *** RV32 Zbc Standard Extension ***
>  clmul      0000101 .......... 001 ..... 0110011 @r
>  clmulh     0000101 .......... 011 ..... 0110011 @r
> --
> 2.25.1
>
>