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[PATCH v2 14/18] target/arm: Implement MVE VCVT between fp and integer
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From: |
Peter Maydell |
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Subject: |
[PATCH v2 14/18] target/arm: Implement MVE VCVT between fp and integer |
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Date: |
Thu, 26 Aug 2021 14:17:21 +0100 |
Implement the MVE "VCVT (between floating-point and integer)" insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/mve.decode | 7 +++++++
target/arm/translate-mve.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index d9fcc42d36d..9a40ff9f43c 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -790,3 +790,10 @@ VCVT_UF_fixed 1111 1111 1 . ...... ... 0 11 . 0 01 . 1
... 0 @vcvt
VCVT_FS_fixed 1110 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt
VCVT_FU_fixed 1111 1111 1 . ...... ... 0 11 . 1 01 . 1 ... 0 @vcvt
+
+# VCVT between floating point and integer (halfprec and single);
+# VCVT_<from><to>, S = signed int, U = unsigned int, F = float
+VCVT_SF 1111 1111 1 . 11 .. 11 ... 0 011 00 1 . 0 ... 0 @1op
+VCVT_UF 1111 1111 1 . 11 .. 11 ... 0 011 01 1 . 0 ... 0 @1op
+VCVT_FS 1111 1111 1 . 11 .. 11 ... 0 011 10 1 . 0 ... 0 @1op
+VCVT_FU 1111 1111 1 . 11 .. 11 ... 0 011 11 1 . 0 ... 0 @1op
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 9269dbc3324..351033af1ec 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -543,6 +543,38 @@ DO_1OP(VQNEG, vqneg)
DO_1OP(VMAXA, vmaxa)
DO_1OP(VMINA, vmina)
+/*
+ * For simple float/int conversions we use the fixed-point
+ * conversion helpers with a zero shift count
+ */
+#define DO_VCVT(INSN, HFN, SFN) \
+ static void gen_##INSN##h(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \
+ { \
+ gen_helper_mve_##HFN(env, qd, qm, tcg_constant_i32(0)); \
+ } \
+ static void gen_##INSN##s(TCGv_ptr env, TCGv_ptr qd, TCGv_ptr qm) \
+ { \
+ gen_helper_mve_##SFN(env, qd, qm, tcg_constant_i32(0)); \
+ } \
+ static bool trans_##INSN(DisasContext *s, arg_1op *a) \
+ { \
+ static MVEGenOneOpFn * const fns[] = { \
+ NULL, \
+ gen_##INSN##h, \
+ gen_##INSN##s, \
+ NULL, \
+ }; \
+ if (!dc_isar_feature(aa32_mve_fp, s)) { \
+ return false; \
+ } \
+ return do_1op(s, a, fns[a->size]); \
+ }
+
+DO_VCVT(VCVT_SF, vcvt_sh, vcvt_sf)
+DO_VCVT(VCVT_UF, vcvt_uh, vcvt_uf)
+DO_VCVT(VCVT_FS, vcvt_hs, vcvt_fs)
+DO_VCVT(VCVT_FU, vcvt_hu, vcvt_fu)
+
/* Narrowing moves: only size 0 and 1 are valid */
#define DO_VMOVN(INSN, FN) \
static bool trans_##INSN(DisasContext *s, arg_1op *a) \
--
2.20.1
- [PATCH v2 07/18] target/arm: Implement MVE scalar fp insns, (continued)
- [PATCH v2 07/18] target/arm: Implement MVE scalar fp insns, Peter Maydell, 2021/08/26
- [PATCH v2 13/18] target/arm: Implement MVE VCVT between floating and fixed point, Peter Maydell, 2021/08/26
- [PATCH v2 08/18] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS, Peter Maydell, 2021/08/26
- [PATCH v2 06/18] target/arm: Implement MVE VMAXNMA and VMINNMA, Peter Maydell, 2021/08/26
- [PATCH v2 12/18] target/arm: Implement MVE fp scalar comparisons, Peter Maydell, 2021/08/26
- [PATCH v2 15/18] target/arm: Implement MVE VCVT with specified rounding mode, Peter Maydell, 2021/08/26
- [PATCH v2 17/18] target/arm: Implement MVE VRINT insns, Peter Maydell, 2021/08/26
- [PATCH v2 10/18] target/arm: Implement MVE FP max/min across vector, Peter Maydell, 2021/08/26
- [PATCH v2 09/18] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode, Peter Maydell, 2021/08/26
- [PATCH v2 14/18] target/arm: Implement MVE VCVT between fp and integer,
Peter Maydell <=
- [PATCH v2 16/18] target/arm: Implement MVE VCVT between single and half precision, Peter Maydell, 2021/08/26
- [PATCH v2 18/18] target/arm: Enable MVE in Cortex-M55, Peter Maydell, 2021/08/26