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[PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_e
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_err() |
Date: |
Wed, 25 Aug 2021 15:02:05 +0200 |
excp/err are temporaries input, so we can replace tcg_const_i32()
calls by tcg_constant_i32() equivalent.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210816205107.2051495-8-f4bug@amsat.org>
---
target/mips/tcg/translate.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index c515a337ebc..93b72c994f2 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1363,12 +1363,9 @@ static inline void restore_cpu_state(CPUMIPSState *env,
DisasContext *ctx)
void generate_exception_err(DisasContext *ctx, int excp, int err)
{
- TCGv_i32 texcp = tcg_const_i32(excp);
- TCGv_i32 terr = tcg_const_i32(err);
save_cpu_state(ctx, 1);
- gen_helper_raise_exception_err(cpu_env, texcp, terr);
- tcg_temp_free_i32(terr);
- tcg_temp_free_i32(texcp);
+ gen_helper_raise_exception_err(cpu_env, tcg_constant_i32(excp),
+ tcg_constant_i32(err));
ctx->base.is_jmp = DISAS_NORETURN;
}
--
2.31.1
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, (continued)
- [PULL 12/28] target/mips: Convert Vr54xx MSA* opcodes to decodetree, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 13/28] target/mips: Document Loongson-3A CPU definitions, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 16/28] target/mips: Remove gen_helper_0e3i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 17/28] target/mips: Remove gen_helper_1e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 21/28] target/mips: Inline gen_helper_0e0i(), Philippe Mathieu-Daudé, 2021/08/25
- [PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_err(),
Philippe Mathieu-Daudé <=
- [PULL 23/28] target/mips: Define gen_helper() macros in translate.h, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 24/28] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 25/28] target/mips: Replace GET_LMASK() macro by get_lmask(32) function, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 26/28] target/mips: Replace GET_LMASK64() macro by get_lmask(64) function, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 27/28] target/mips: Store CP0_Config0 in DisasContext, Philippe Mathieu-Daudé, 2021/08/25
- [PULL 28/28] target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian(), Philippe Mathieu-Daudé, 2021/08/25
- Re: [PULL 00/28] MIPS patches for 2021-08-25, Peter Maydell, 2021/08/26