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[PULL 17/44] target/arm: Implement MVE VPSEL
From: |
Peter Maydell |
Subject: |
[PULL 17/44] target/arm: Implement MVE VPSEL |
Date: |
Wed, 25 Aug 2021 11:35:07 +0100 |
Implement the MVE VPSEL insn, which sets each byte of the destination
vector Qd to the byte from either Qn or Qm depending on the value of
the corresponding bit in VPR.P0.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-mve.h | 2 ++
target/arm/mve.decode | 7 +++++--
target/arm/mve_helper.c | 19 +++++++++++++++++++
target/arm/translate-mve.c | 2 ++
4 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 4f9903e66ef..16c4c3b8f61 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -82,6 +82,8 @@ DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr,
ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vpsel, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vaddw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index ef708ba80ff..4bd20a9a319 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -468,8 +468,11 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100
rdm:4 qd=%qd
# effectively "VCMP then VPST". A plain "VCMP" has a mask field of zero.
VCMPEQ 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 0 @vcmp
VCMPNE 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 0 @vcmp
-VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp
-VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp
+{
+ VPSEL 1111 1110 0 . 11 ... 1 ... 0 1111 . 0 . 0 ... 1 @2op_nosz
+ VCMPCS 1111 1110 0 . .. ... 1 ... 0 1111 0 0 . 0 ... 1 @vcmp
+ VCMPHI 1111 1110 0 . .. ... 1 ... 0 1111 1 0 . 0 ... 1 @vcmp
+}
VCMPGE 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 0 @vcmp
VCMPLT 1111 1110 0 . .. ... 1 ... 1 1111 1 0 . 0 ... 0 @vcmp
VCMPGT 1111 1110 0 . .. ... 1 ... 1 1111 0 0 . 0 ... 1 @vcmp
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 1a021a9a817..03171766b57 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -1842,3 +1842,22 @@ DO_VCMP_S(vcmpge, DO_GE)
DO_VCMP_S(vcmplt, DO_LT)
DO_VCMP_S(vcmpgt, DO_GT)
DO_VCMP_S(vcmple, DO_LE)
+
+void HELPER(mve_vpsel)(CPUARMState *env, void *vd, void *vn, void *vm)
+{
+ /*
+ * Qd[n] = VPR.P0[n] ? Qn[n] : Qm[n]
+ * but note that whether bytes are written to Qd is still subject
+ * to (all forms of) predication in the usual way.
+ */
+ uint64_t *d = vd, *n = vn, *m = vm;
+ uint16_t mask = mve_element_mask(env);
+ uint16_t p0 = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0);
+ unsigned e;
+ for (e = 0; e < 16 / 8; e++, mask >>= 8, p0 >>= 8) {
+ uint64_t r = m[H8(e)];
+ mergemask(&r, n[H8(e)], p0);
+ mergemask(&d[H8(e)], r, mask);
+ }
+ mve_advance_vpt(env);
+}
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 6c6f159aa3e..aa38218e08f 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -376,6 +376,8 @@ DO_LOGIC(VORR, gen_helper_mve_vorr)
DO_LOGIC(VORN, gen_helper_mve_vorn)
DO_LOGIC(VEOR, gen_helper_mve_veor)
+DO_LOGIC(VPSEL, gen_helper_mve_vpsel)
+
#define DO_2OP(INSN, FN) \
static bool trans_##INSN(DisasContext *s, arg_2op *a) \
{ \
--
2.20.1
- [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements, (continued)
- [PULL 11/44] target/arm: Fix VLDRB/H/W for predicated elements, Peter Maydell, 2021/08/25
- [PULL 13/44] target/arm: Implement MVE incrementing/decrementing dup insns, Peter Maydell, 2021/08/25
- [PULL 12/44] target/arm: Implement MVE VMULL (polynomial), Peter Maydell, 2021/08/25
- [PULL 14/44] target/arm: Factor out gen_vpst(), Peter Maydell, 2021/08/25
- [PULL 16/44] target/arm: Implement MVE integer vector-vs-scalar comparisons, Peter Maydell, 2021/08/25
- [PULL 15/44] target/arm: Implement MVE integer vector comparisons, Peter Maydell, 2021/08/25
- [PULL 19/44] target/arm: Implement MVE shift-by-scalar, Peter Maydell, 2021/08/25
- [PULL 18/44] target/arm: Implement MVE VMLAS, Peter Maydell, 2021/08/25
- [PULL 20/44] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats, Peter Maydell, 2021/08/25
- [PULL 22/44] target/arm: Implement MVE VABAV, Peter Maydell, 2021/08/25
- [PULL 17/44] target/arm: Implement MVE VPSEL,
Peter Maydell <=
- [PULL 26/44] target/arm: Implement MVE VMLA, Peter Maydell, 2021/08/25
- [PULL 21/44] target/arm: Implement MVE integer min/max across vector, Peter Maydell, 2021/08/25
- [PULL 23/44] target/arm: Implement MVE narrowing moves, Peter Maydell, 2021/08/25
- [PULL 25/44] target/arm: Implement MVE VMLADAV and VMLSLDAV, Peter Maydell, 2021/08/25
- [PULL 27/44] target/arm: Implement MVE saturating doubling multiply accumulates, Peter Maydell, 2021/08/25
- [PULL 31/44] target/arm: Implement MVE VPNOT, Peter Maydell, 2021/08/25
- [PULL 29/44] target/arm: Implement MVE VMAXA, VMINA, Peter Maydell, 2021/08/25
- [PULL 30/44] target/arm: Implement MVE VMOV to/from 2 general-purpose registers, Peter Maydell, 2021/08/25
- [PULL 28/44] target/arm: Implement MVE VQABS, VQNEG, Peter Maydell, 2021/08/25
- [PULL 33/44] target/arm: Implement MVE scatter-gather insns, Peter Maydell, 2021/08/25