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Re: [PATCH v4 03/21] target/riscv: Clean up division helpers
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v4 03/21] target/riscv: Clean up division helpers |
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Date: |
Mon, 23 Aug 2021 16:09:29 +1000 |
On Sat, Aug 21, 2021 at 3:48 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Utilize the condition in the movcond more; this allows some of
> the setcond that were feeding into movcond to be removed.
> Do not write into source1 and source2. Re-name "condN" to "tempN"
> and use the temporaries for more than holding conditions.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 160 ++++++++++++++++++++-------------------
> 1 file changed, 84 insertions(+), 76 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 20a55c92fb..147b9c2f68 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -213,106 +213,114 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
>
> static void gen_div(TCGv ret, TCGv source1, TCGv source2)
> {
> - TCGv cond1, cond2, zeroreg, resultopt1;
> + TCGv temp1, temp2, zero, one, mone, min;
> +
> + temp1 = tcg_temp_new();
> + temp2 = tcg_temp_new();
> + zero = tcg_constant_tl(0);
> + one = tcg_constant_tl(1);
> + mone = tcg_constant_tl(-1);
> + min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
> +
> /*
> - * Handle by altering args to tcg_gen_div to produce req'd results:
> - * For overflow: want source1 in source1 and 1 in source2
> - * For div by zero: want -1 in source1 and 1 in source2 -> -1 result
> + * If overflow, set temp2 to 1, else source2.
> + * This produces the required result of min.
> */
> - cond1 = tcg_temp_new();
> - cond2 = tcg_temp_new();
> - zeroreg = tcg_constant_tl(0);
> - resultopt1 = tcg_temp_new();
> + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
> + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
> + tcg_gen_and_tl(temp1, temp1, temp2);
> + tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp1, zero, one, source2);
>
> - tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L));
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
> - ((target_ulong)1) << (TARGET_LONG_BITS - 1));
> - tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */
> - /* if div by zero, set source1 to -1, otherwise don't change */
> - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1,
> - resultopt1);
> - /* if overflow or div by zero, set source2 to 1, else don't change */
> - tcg_gen_or_tl(cond1, cond1, cond2);
> - tcg_gen_movi_tl(resultopt1, (target_ulong)1);
> - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
> - resultopt1);
> - tcg_gen_div_tl(ret, source1, source2);
> + /*
> + * If div by zero, set temp1 to -1 and temp2 to 1 to
> + * produce the required result of -1.
> + */
> + tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
> + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, temp2);
>
> - tcg_temp_free(cond1);
> - tcg_temp_free(cond2);
> - tcg_temp_free(resultopt1);
> + tcg_gen_div_tl(ret, temp1, temp2);
> +
> + tcg_temp_free(temp1);
> + tcg_temp_free(temp2);
> }
>
> static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
> {
> - TCGv cond1, zeroreg, resultopt1;
> - cond1 = tcg_temp_new();
> + TCGv temp1, temp2, zero, one, max;
>
> - zeroreg = tcg_constant_tl(0);
> - resultopt1 = tcg_temp_new();
> + temp1 = tcg_temp_new();
> + temp2 = tcg_temp_new();
> + zero = tcg_constant_tl(0);
> + one = tcg_constant_tl(1);
> + max = tcg_constant_tl(~0);
>
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
> - tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
> - tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1,
> - resultopt1);
> - tcg_gen_movi_tl(resultopt1, (target_ulong)1);
> - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
> - resultopt1);
> - tcg_gen_divu_tl(ret, source1, source2);
> + /*
> + * If div by zero, set temp1 to max and temp2 to 1 to
> + * produce the required result of max.
> + */
> + tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
> + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
> + tcg_gen_divu_tl(ret, temp1, temp2);
>
> - tcg_temp_free(cond1);
> - tcg_temp_free(resultopt1);
> + tcg_temp_free(temp1);
> + tcg_temp_free(temp2);
> }
>
> static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
> {
> - TCGv cond1, cond2, zeroreg, resultopt1;
> + TCGv temp1, temp2, zero, one, mone, min;
>
> - cond1 = tcg_temp_new();
> - cond2 = tcg_temp_new();
> - zeroreg = tcg_constant_tl(0);
> - resultopt1 = tcg_temp_new();
> + temp1 = tcg_temp_new();
> + temp2 = tcg_temp_new();
> + zero = tcg_constant_tl(0);
> + one = tcg_constant_tl(1);
> + mone = tcg_constant_tl(-1);
> + min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
>
> - tcg_gen_movi_tl(resultopt1, 1L);
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1);
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1,
> - (target_ulong)1 << (TARGET_LONG_BITS - 1));
> - tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */
> - /* if overflow or div by zero, set source2 to 1, else don't change */
> - tcg_gen_or_tl(cond2, cond1, cond2);
> - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2,
> - resultopt1);
> - tcg_gen_rem_tl(resultopt1, source1, source2);
> - /* if div by zero, just return the original dividend */
> - tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
> - source1);
> + /*
> + * If overflow, set temp1 to 0, else source1.
> + * This avoids a possible host trap, and produces the required result of
> 0.
> + */
> + tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
> + tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
> + tcg_gen_and_tl(temp1, temp1, temp2);
> + tcg_gen_movcond_tl(TCG_COND_NE, temp1, temp1, zero, zero, source1);
>
> - tcg_temp_free(cond1);
> - tcg_temp_free(cond2);
> - tcg_temp_free(resultopt1);
> + /*
> + * If div by zero, set temp2 to 1, else source2.
> + * This avoids a possible host trap, but produces an incorrect result.
> + */
> + tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
> +
> + tcg_gen_rem_tl(temp1, temp1, temp2);
> +
> + /* If div by zero, the required result is the original dividend. */
> + tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp1);
> +
> + tcg_temp_free(temp1);
> + tcg_temp_free(temp2);
> }
>
> static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
> {
> - TCGv cond1, zeroreg, resultopt1;
> - cond1 = tcg_temp_new();
> - zeroreg = tcg_constant_tl(0);
> - resultopt1 = tcg_temp_new();
> + TCGv temp, zero, one;
>
> - tcg_gen_movi_tl(resultopt1, (target_ulong)1);
> - tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
> - tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2,
> - resultopt1);
> - tcg_gen_remu_tl(resultopt1, source1, source2);
> - /* if div by zero, just return the original dividend */
> - tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1,
> - source1);
> + temp = tcg_temp_new();
> + zero = tcg_constant_tl(0);
> + one = tcg_constant_tl(1);
>
> - tcg_temp_free(cond1);
> - tcg_temp_free(resultopt1);
> + /*
> + * If div by zero, set temp to 1, else source2.
> + * This avoids a possible host trap, but produces an incorrect result.
> + */
> + tcg_gen_movcond_tl(TCG_COND_EQ, temp, source2, zero, one, source2);
> +
> + tcg_gen_remu_tl(temp, source1, temp);
> +
> + /* If div by zero, the required result is the original dividend. */
> + tcg_gen_movcond_tl(TCG_COND_EQ, ret, source2, zero, source1, temp);
> +
> + tcg_temp_free(temp);
> }
>
> static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
> --
> 2.25.1
>
>
- [PATCH v4 00/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/20
- [PATCH v4 02/21] tests/tcg/riscv64: Add test for division, Richard Henderson, 2021/08/20
- [PATCH v4 04/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Richard Henderson, 2021/08/20
- [PATCH v4 06/21] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/20
- [PATCH v4 03/21] target/riscv: Clean up division helpers, Richard Henderson, 2021/08/20
- [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/20
- [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/20
- [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/20
- [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/20
- [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/20
- [PATCH v4 01/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/20
- [PATCH v4 07/21] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/20
- [PATCH v4 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/20