Re: [PATCH v3 08/21] target/riscv: Move gen

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Re: [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM

From:	Alistair Francis
Subject:	Re: [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM
Date:	Fri, 20 Aug 2021 11:35:11 +1000

On Thu, Aug 19, 2021 at 7:08 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Move these helpers near their use by the trans_*
> functions within insn_trans/trans_rvm.c.inc.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c                | 115 ------------------------
>  target/riscv/insn_trans/trans_rvm.c.inc | 115 ++++++++++++++++++++++++
>  2 files changed, 115 insertions(+), 115 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index bc40b9c701..7fbacfa6ee 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -249,121 +249,6 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, 
> TCGv t)
>      }
>  }
>
> -static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> -    TCGv rl = tcg_temp_new();
> -    TCGv rh = tcg_temp_new();
> -
> -    tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
> -    /* fix up for one negative */
> -    tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
> -    tcg_gen_and_tl(rl, rl, arg2);
> -    tcg_gen_sub_tl(ret, rh, rl);
> -
> -    tcg_temp_free(rl);
> -    tcg_temp_free(rh);
> -}
> -
> -static void gen_div(TCGv ret, TCGv source1, TCGv source2)
> -{
> -    TCGv temp1, temp2, zero, one, mone, min;
> -
> -    /*
> -     * Handle by altering args to tcg_gen_div to produce req'd results:
> -     * For overflow: want source1 in temp1 and 1 in temp2
> -     * For div by zero: want -1 in temp1 and 1 in temp2 -> -1 result
> -     */
> -    temp1 = tcg_temp_new();
> -    temp2 = tcg_temp_new();
> -    zero = tcg_constant_tl(0);
> -    one = tcg_constant_tl(1);
> -    mone = tcg_constant_tl(-1);
> -    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
> -
> -    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
> -    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
> -    tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
> -    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
> -    tcg_gen_or_tl(temp2, temp2, temp1);  /* temp2 = overflow | div0 */
> -
> -    /* if div by zero, set temp1 to -1, else source1. */
> -    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
> -
> -    /* if overflow or div by zero, set temp2 to 1, else source2 */
> -    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2);
> -
> -    tcg_gen_div_tl(ret, temp1, temp2);
> -
> -    tcg_temp_free(temp1);
> -    tcg_temp_free(temp2);
> -}
> -
> -static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
> -{
> -    TCGv temp1, temp2, zero, one, max;
> -
> -    temp1 = tcg_temp_new();
> -    temp2 = tcg_temp_new();
> -    zero = tcg_constant_tl(0);
> -    one = tcg_constant_tl(1);
> -    max = tcg_constant_tl(~0);
> -
> -    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
> -    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
> -    tcg_gen_divu_tl(ret, temp1, temp2);
> -
> -    tcg_temp_free(temp1);
> -    tcg_temp_free(temp2);
> -}
> -
> -static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
> -{
> -    TCGv temp1, temp2, zero, one, mone, min;
> -
> -    temp1 = tcg_temp_new();
> -    temp2 = tcg_temp_new();
> -    zero = tcg_constant_tl(0);
> -    one = tcg_constant_tl(1);
> -    mone = tcg_constant_tl(-1);
> -    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
> -
> -    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
> -    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
> -    tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
> -    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
> -    tcg_gen_or_tl(temp2, temp2, temp1);  /* temp2 = overflow | div0 */
> -
> -    /*
> -     * if overflow or div by zero, set temp2 to 1, else source2
> -     * this automatically takes care of returning the original
> -     * dividend for div by zero.
> -     */
> -    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2);
> -
> -    tcg_gen_rem_tl(ret, source1, temp2);
> -
> -    tcg_temp_free(temp1);
> -    tcg_temp_free(temp2);
> -}
> -
> -static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
> -{
> -    TCGv temp2, zero, one;
> -
> -    temp2 = tcg_temp_new();
> -    zero = tcg_constant_tl(0);
> -    one = tcg_constant_tl(1);
> -
> -    /*
> -     * if div by zero, set temp2 to 1, else source2
> -     * this automatically takes care of returning the original dividend.
> -     */
> -    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
> -    tcg_gen_remu_tl(ret, source1, temp2);
> -
> -    tcg_temp_free(temp2);
> -}
> -
>  static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
>  {
>      target_ulong next_pc;
> diff --git a/target/riscv/insn_trans/trans_rvm.c.inc 
> b/target/riscv/insn_trans/trans_rvm.c.inc
> index 80552be7a3..28bdfbca70 100644
> --- a/target/riscv/insn_trans/trans_rvm.c.inc
> +++ b/target/riscv/insn_trans/trans_rvm.c.inc
> @@ -39,6 +39,21 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
>      return gen_arith(ctx, a, EXT_NONE, gen_mulh);
>  }
>
> +static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> +    TCGv rl = tcg_temp_new();
> +    TCGv rh = tcg_temp_new();
> +
> +    tcg_gen_mulu2_tl(rl, rh, arg1, arg2);
> +    /* fix up for one negative */
> +    tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1);
> +    tcg_gen_and_tl(rl, rl, arg2);
> +    tcg_gen_sub_tl(ret, rh, rl);
> +
> +    tcg_temp_free(rl);
> +    tcg_temp_free(rh);
> +}
> +
>  static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
>  {
>      REQUIRE_EXT(ctx, RVM);
> @@ -59,24 +74,124 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
>      return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
>  }
>
> +static void gen_div(TCGv ret, TCGv source1, TCGv source2)
> +{
> +    TCGv temp1, temp2, zero, one, mone, min;
> +
> +    /*
> +     * Handle by altering args to tcg_gen_div to produce req'd results:
> +     * For overflow: want source1 in temp1 and 1 in temp2
> +     * For div by zero: want -1 in temp1 and 1 in temp2 -> -1 result
> +     */
> +    temp1 = tcg_temp_new();
> +    temp2 = tcg_temp_new();
> +    zero = tcg_constant_tl(0);
> +    one = tcg_constant_tl(1);
> +    mone = tcg_constant_tl(-1);
> +    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
> +
> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
> +    tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
> +    tcg_gen_or_tl(temp2, temp2, temp1);  /* temp2 = overflow | div0 */
> +
> +    /* if div by zero, set temp1 to -1, else source1. */
> +    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, mone, source1);
> +
> +    /* if overflow or div by zero, set temp2 to 1, else source2 */
> +    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2);
> +
> +    tcg_gen_div_tl(ret, temp1, temp2);
> +
> +    tcg_temp_free(temp1);
> +    tcg_temp_free(temp2);
> +}
> +
>  static bool trans_div(DisasContext *ctx, arg_div *a)
>  {
>      REQUIRE_EXT(ctx, RVM);
>      return gen_arith(ctx, a, EXT_SIGN, gen_div);
>  }
>
> +static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
> +{
> +    TCGv temp1, temp2, zero, one, max;
> +
> +    temp1 = tcg_temp_new();
> +    temp2 = tcg_temp_new();
> +    zero = tcg_constant_tl(0);
> +    one = tcg_constant_tl(1);
> +    max = tcg_constant_tl(~0);
> +
> +    tcg_gen_movcond_tl(TCG_COND_EQ, temp1, source2, zero, max, source1);
> +    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
> +    tcg_gen_divu_tl(ret, temp1, temp2);
> +
> +    tcg_temp_free(temp1);
> +    tcg_temp_free(temp2);
> +}
> +
>  static bool trans_divu(DisasContext *ctx, arg_divu *a)
>  {
>      REQUIRE_EXT(ctx, RVM);
>      return gen_arith(ctx, a, EXT_ZERO, gen_divu);
>  }
>
> +static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
> +{
> +    TCGv temp1, temp2, zero, one, mone, min;
> +
> +    temp1 = tcg_temp_new();
> +    temp2 = tcg_temp_new();
> +    zero = tcg_constant_tl(0);
> +    one = tcg_constant_tl(1);
> +    mone = tcg_constant_tl(-1);
> +    min = tcg_constant_tl(1ull << (TARGET_LONG_BITS - 1));
> +
> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp1, source1, min);
> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, mone);
> +    tcg_gen_and_tl(temp1, temp1, temp2); /* temp1 = overflow */
> +    tcg_gen_setcond_tl(TCG_COND_EQ, temp2, source2, zero); /* temp2 = div0 */
> +    tcg_gen_or_tl(temp2, temp2, temp1);  /* temp2 = overflow | div0 */
> +
> +    /*
> +     * if overflow or div by zero, set temp2 to 1, else source2
> +     * this automatically takes care of returning the original
> +     * dividend for div by zero.
> +     */
> +    tcg_gen_movcond_tl(TCG_COND_NE, temp2, temp2, zero, one, source2);
> +
> +    tcg_gen_rem_tl(ret, source1, temp2);
> +
> +    tcg_temp_free(temp1);
> +    tcg_temp_free(temp2);
> +}
> +
>  static bool trans_rem(DisasContext *ctx, arg_rem *a)
>  {
>      REQUIRE_EXT(ctx, RVM);
>      return gen_arith(ctx, a, EXT_SIGN, gen_rem);
>  }
>
> +static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
> +{
> +    TCGv temp2, zero, one;
> +
> +    temp2 = tcg_temp_new();
> +    zero = tcg_constant_tl(0);
> +    one = tcg_constant_tl(1);
> +
> +    /*
> +     * if div by zero, set temp2 to 1, else source2
> +     * this automatically takes care of returning the original dividend.
> +     */
> +    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, source2, zero, one, source2);
> +    tcg_gen_remu_tl(ret, source1, temp2);
> +
> +    tcg_temp_free(temp2);
> +}
> +
>  static bool trans_remu(DisasContext *ctx, arg_remu *a)
>  {
>      REQUIRE_EXT(ctx, RVM);
> --
> 2.25.1
>
>

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Re: [PATCH v3 02/21] target/riscv: Clean up division helpers, (continued)
- [PATCH v3 01/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/19
- [PATCH v3 04/21] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/19
  - Re: [PATCH v3 04/21] target/riscv: Introduce DisasExtend and new helpers, Bin Meng, 2021/08/19
- [PATCH v3 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Richard Henderson, 2021/08/19
- [PATCH v3 05/21] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/19
- [PATCH v3 06/21] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/19
- [PATCH v3 07/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/19
- [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/19
  - Re: [PATCH v3 08/21] target/riscv: Move gen_* helpers for RVM, Alistair Francis <=
- [PATCH v3 09/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/19
- [PATCH v3 10/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/19
- [PATCH v3 12/21] target/riscv: Add gen_greviw, Richard Henderson, 2021/08/19
- [PATCH v3 11/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/19
- [PATCH v3 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/19
- [PATCH v3 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/19
- [PATCH v3 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/19
- [PATCH v3 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/19
- [PATCH v3 16/21] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/19
- [PATCH v3 18/21] target/riscv: Use {get,dest}_gpr for RVF, Richard Henderson, 2021/08/19

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