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Re: [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith*
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith* |
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Date: |
Thu, 19 Aug 2021 10:42:08 +0800 |
On Wed, Aug 18, 2021 at 5:23 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Most arithmetic does not require extending the inputs.
> Exceptions include division, comparison and minmax.
>
> Begin using ctx->w, which allows elimination of gen_addw,
> gen_subw, gen_mulw.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/translate.c | 69 +++++++------------------
> target/riscv/insn_trans/trans_rvb.c.inc | 30 +++++------
> target/riscv/insn_trans/trans_rvi.c.inc | 39 ++++++++------
> target/riscv/insn_trans/trans_rvm.c.inc | 16 +++---
> 4 files changed, 64 insertions(+), 90 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, (continued)
- [PATCH v2 03/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Richard Henderson, 2021/08/17
- [PATCH v2 04/21] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/17
- [PATCH v2 05/21] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/17
- [PATCH v2 06/21] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/17
- [PATCH v2 07/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/17
- [PATCH v2 08/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/17