Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs prope

qemu-devel

From:	Richard Henderson
Subject:	Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties
Date:	Wed, 18 Aug 2021 12:39:19 -1000
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0

On 8/18/21 10:32 AM, Philipp Tomsich wrote:

+++ b/target/riscv/cpu.h
@@ -67,7 +67,6 @@
  #define RVS RV('S')
  #define RVU RV('U')
  #define RVH RV('H')
-#define RVB RV('B')

This patch does not compile by itself, because RVB is still used ininsn_trans/trans_rvb.c.inc.

r~

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[PATCH v2 0/3] target/riscv: Update QEmu for Zb[abcs] 1.0.0, Philipp Tomsich, 2021/08/18
- [PATCH v2 2/3] target/riscv: update Zb[abcs] to 1.0.0 (public review) specification, Philipp Tomsich, 2021/08/18
  - Re: [PATCH v2 2/3] target/riscv: update Zb[abcs] to 1.0.0 (public review) specification, Richard Henderson, 2021/08/18
- [PATCH v2 3/3] disas/riscv: Add Zb[abcs] instructions, Philipp Tomsich, 2021/08/18
- [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/08/18
  - Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Richard Henderson <=
    - Re: [PATCH v2 1/3] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties, Philipp Tomsich, 2021/08/18