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[PATCH v3 08/16] tcg/mips: Unset TCG_TARGET_HAS_direct_jump
From: |
Richard Henderson |
Subject: |
[PATCH v3 08/16] tcg/mips: Unset TCG_TARGET_HAS_direct_jump |
Date: |
Wed, 18 Aug 2021 10:19:23 -1000 |
Only use indirect jumps. Finish weaning away from the
unique alignment requirements for code_gen_buffer.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.h | 12 +++++-------
tcg/mips/tcg-target.c.inc | 23 +++++------------------
2 files changed, 10 insertions(+), 25 deletions(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index c34cccebd3..28c42e23e1 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -39,11 +39,7 @@
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
#define TCG_TARGET_NB_REGS 32
-/*
- * We have a 256MB branch region, but leave room to make sure the
- * main executable is also within that region.
- */
-#define MAX_CODE_GEN_BUFFER_SIZE (128 * MiB)
+#define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
typedef enum {
TCG_REG_ZERO = 0,
@@ -136,7 +132,7 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_muluh_i32 1
#define TCG_TARGET_HAS_mulsh_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
-#define TCG_TARGET_HAS_direct_jump 1
+#define TCG_TARGET_HAS_direct_jump 0
#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_add2_i32 0
@@ -207,7 +203,9 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1
-void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
+/* not defined -- call should be eliminated at compile time */
+void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t)
+ QEMU_ERROR("code path is reachable");
#define TCG_TARGET_NEED_LDST_LABELS
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index c65c4ee1f8..1c5c0854c7 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1977,17 +1977,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
case INDEX_op_goto_tb:
- if (s->tb_jmp_insn_offset) {
- /* direct jump method */
- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
- /* Avoid clobbering the address during retranslation. */
- tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff));
- } else {
- /* indirect jump method */
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
- (uintptr_t)(s->tb_jmp_target_addr + a0));
- tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
- }
+ /* indirect jump method */
+ tcg_debug_assert(s->tb_jmp_insn_offset == 0);
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO,
+ (uintptr_t)(s->tb_jmp_target_addr + a0));
+ tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
tcg_out_nop(s);
set_jmp_reset_offset(s, a0);
break;
@@ -2861,13 +2855,6 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
}
-void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
- uintptr_t jmp_rw, uintptr_t addr)
-{
- qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2));
- flush_idcache_range(jmp_rx, jmp_rw, 4);
-}
-
typedef struct {
DebugFrameHeader h;
uint8_t fde_def_cfa[4];
--
2.25.1
- [PATCH v3 00/16] tcg/mips: Unaligned access and other cleanup, Richard Henderson, 2021/08/18
- [PATCH v3 01/16] tcg/mips: Support unaligned access for user-only, Richard Henderson, 2021/08/18
- [PATCH v3 02/16] tcg/mips: Support unaligned access for softmmu, Richard Henderson, 2021/08/18
- [PATCH v3 06/16] tcg/mips: Unify TCG_GUEST_BASE_REG tests, Richard Henderson, 2021/08/18
- [PATCH v3 08/16] tcg/mips: Unset TCG_TARGET_HAS_direct_jump,
Richard Henderson <=
- [PATCH v3 04/16] tcg/mips: Move TCG_AREG0 to S8, Richard Henderson, 2021/08/18
- [PATCH v3 07/16] tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr, Richard Henderson, 2021/08/18
- [PATCH v3 05/16] tcg/mips: Move TCG_GUEST_BASE_REG to S7, Richard Henderson, 2021/08/18
- [PATCH v3 11/16] tcg/mips: Split out tcg_out_movi_one, Richard Henderson, 2021/08/18
- [PATCH v3 03/16] tcg/mips: Drop inline markers, Richard Henderson, 2021/08/18
- [PATCH v3 09/16] tcg/mips: Drop special alignment for code_gen_buffer, Richard Henderson, 2021/08/18