Re: [PATCH v4 2/2] arm/monitor: Add support for 'info tlb' command

[Bin Meng]

On Wed, Aug 18, 2021 at 8:54 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Wed, 18 Aug 2021 at 13:00, Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > On Wed, Aug 18, 2021 at 7:48 PM NDNF <arkaisp2021@gmail.com> wrote:
> > >
> > > This adds hmp 'info tlb' command support for the arm platform.
> > > The limitation is that this only implements a page walker for
> > > ARMv8-A AArch64 Long Descriptor format, 32bit addressing is
> > > not supported yet.
> > >
> > > Signed-off-by: Changbin Du <changbin.du@gmail.com>
> > > Signed-off-by: Ivanov Arkady <arkaisp2021@gmail.com>
> > > ---
> > >  hmp-commands-info.hx |    3 +
> > >  target/arm/monitor.c |  170 
> > > ++++++++++++++++++++++++++++++++++++++++++++++++++
> > >  2 files changed, 172 insertions(+), 1 deletion(-)
> > >
> >
> > I believe this is not TLB on ARM, but PTE?
> >
> > RISC-V implemented a "info mem" for page table walk.
>
> We call our "give page table walk" monitor command "info tlb"
> for some reason (probably historical). From the docs:
> https://qemu-project.gitlab.io/qemu/system/monitor.html
>   info tlb
>       Show virtual to physical memory mappings
>   info mem
>       Show the active virtual memory mappings.
>
> Looking at x86's output, "info tlb" gives lines like this:

I don't know why x86 provides 2 almost the same things.

>
> ffffffffc04f6000: 00000000b2576000 -G-DA----
> ffffffffc04f7000: 00000000b2579000 -G-DA----
> ffffffffc04f8000: 00000000bac74000 XG-DA----
> ffffffffc04f9000: 00000000b258b000 XG-DA----
> ffffffffc04fa000: 00000000b248b000 XG-DA---W
> ffffffffc04fb000: 00000000b2431000 XG-DA---W
> ffffffffc0502000: 00000000bb69c000 -G-DA----
> ffffffffc0503000: 00000000b27d3000 XG-DA----
>

Naming it to "tlb" really confuses people. On ppce500, "info tlb"
gives the real processor TLBs, not the PTEs.

(qemu) info tlb

TLB0:
Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123

TLB1:
Effective          Physical           Size TID   TS SRWX URWX WIMGE U0123
0x00000000e0000000 0x0000000fe0000000   1M 0     0  SRW-U--- -I-G- U----
0x0000000000000000 0x0000000000000000  64M 0     0  SRWXU--- --M-- U----
0x0000000004000000 0x0000000004000000  64M 0     0  SRWXU--- --M-- U----
0x00000000f0000000 0x0000000f00000000  64M 0     0  SRW-U--- -I-G- U----
0x0000000080000000 0x0000000c00000000 256M 0     0  SRW-U--- -I-G- U----
0x0000000090000000 0x0000000c10000000 256M 0     0  SRW-U--- -I-G- U----
0x00000000a0000000 0x0000000fe1000000  64K 0     0  SRW-U--- -I-G- U----
0x00000000f4000000 0x0000000f04000000  64M 0     0  SRW-U--- -I-G- U----

So we are unfortunately inconsistent among these arches that support "info tlb".

> which is a dump of the page table, with one line per page,
> giving the vaddr, the physaddr and associated flag information.
>
> "info mem" gives lines like this:
>
> ffffffffc04f6000-ffffffffc04fa000 0000000000004000 -r-
> ffffffffc04fa000-ffffffffc04fc000 0000000000002000 -rw
> ffffffffc0502000-ffffffffc0504000 0000000000002000 -r-
>
> which just give "this range of virtual addresses of this
> length have these permissions". You can see that it
> coalesces multiple adjacent pages with the same permissions
> into a single line.
>
> The only architectures which implement "info mem"
> are i386 and riscv. If riscv has given the command
> different semantics to i386 that would be unfortunate.
>
> "info tlb" is implemented by i386, m68k, nios2, ppc, sh4,
> sparc, xtensa.
>
> It's not clear to me that "info mem" is all that useful -- you
> can figure out the same info from "info tlb".

Yes. But I feel "info mem" is more a suitable name than "info tlb"
unless we are really printing the TLB.

Regards,
Bin