[PATCH v2 55/55] target/sh4: Implement prctl_unalign

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[PATCH v2 55/55] target/sh4: Implement prctl_unalign_sigbus

From:	Richard Henderson
Subject:	[PATCH v2 55/55] target/sh4: Implement prctl_unalign_sigbus
Date:	Mon, 2 Aug 2021 18:14:43 -1000

Leave TARGET_ALIGNED_ONLY set, but use the new CPUState
flag to set MO_UNALN for the instructions that the kernel
handles in the unaligned trap.

The Linux kernel does not handle all memory operations: no
floating-point and no MAC.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sh4/cpu.h       |  4 ++++
 hw/core/cpu-user.c     |  2 +-
 linux-user/syscall.c   |  2 +-
 target/sh4/translate.c | 50 ++++++++++++++++++++++++++++--------------
 4 files changed, 40 insertions(+), 18 deletions(-)

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index a9191951f8..5f2dc551e3 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -83,6 +83,7 @@
 #define DELAY_SLOT_RTE         (1 << 2)
 
 #define TB_FLAG_PENDING_MOVCA  (1 << 3)
+#define TB_FLAG_UNALIGN        (1 << 4)
 
 #define GUSA_SHIFT             4
 #ifdef CONFIG_USER_ONLY
@@ -376,6 +377,9 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, 
target_ulong *pc,
             | (env->sr & ((1u << SR_MD) | (1u << SR_RB)))      /* Bits 29-30 */
             | (env->sr & (1u << SR_FD))                        /* Bit 15 */
             | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+#ifdef CONFIG_USER_ONLY
+    *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
 }
 
 #endif /* SH4_CPU_H */
diff --git a/hw/core/cpu-user.c b/hw/core/cpu-user.c
index 6a5edcfb77..0ad009f186 100644
--- a/hw/core/cpu-user.c
+++ b/hw/core/cpu-user.c
@@ -24,7 +24,7 @@ static Property cpu_useronly_props[] = {
      * up its memory. The default if no link is set up is to use the
      * system address space.
      */
-#if defined(TARGET_ALPHA) || defined(TARGET_HPPA)
+#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) || defined(TARGET_SH4)
     DEFINE_PROP_BOOL("prctl-unalign-sigbus", CPUState,
                      prctl_unalign_sigbus, false),
 #endif
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 836a7eaee2..784ced821d 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -6644,7 +6644,7 @@ static abi_long do_prctl(CPUArchState *env, abi_long 
option, abi_long arg2,
      * We only implement PR_UNALIGN_SIGBUS, and only for those targets
      * who have had their translator updated to insert MO_ALIGN.
      */
-#if defined(TARGET_ALPHA) || defined(TARGET_HPPA)
+#if defined(TARGET_ALPHA) || defined(TARGET_HPPA) || defined(TARGET_SH4)
     case PR_GET_UNALIGN:
         {
             CPUState *cs = env_cpu(env);
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 8704fea1ca..58ec6e8ac9 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -50,8 +50,10 @@ typedef struct DisasContext {
 
 #if defined(CONFIG_USER_ONLY)
 #define IS_USER(ctx) 1
+#define UNALIGN(C)   (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : 0)
 #else
 #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
+#define UNALIGN(C)   0
 #endif
 
 /* Target-specific values for ctx->base.is_jmp.  */
@@ -499,7 +501,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
-            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+                                MO_TEUL | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
@@ -507,7 +510,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
-            tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+            tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+                                MO_TESL | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
@@ -562,19 +566,23 @@ static void _decode_opc(DisasContext * ctx)
         tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
        return;
     case 0x2001:               /* mov.w Rm,@Rn */
-        tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
+        tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+                            MO_TEUW | UNALIGN(ctx));
        return;
     case 0x2002:               /* mov.l Rm,@Rn */
-        tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
+        tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx,
+                            MO_TEUL | UNALIGN(ctx));
        return;
     case 0x6000:               /* mov.b @Rm,Rn */
         tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
        return;
     case 0x6001:               /* mov.w @Rm,Rn */
-        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+                            MO_TESW | UNALIGN(ctx));
        return;
     case 0x6002:               /* mov.l @Rm,Rn */
-        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+                            MO_TESL | UNALIGN(ctx));
        return;
     case 0x2004:               /* mov.b Rm,@-Rn */
        {
@@ -590,7 +598,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_subi_i32(addr, REG(B11_8), 2);
-            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+                                MO_TEUW | UNALIGN(ctx));
            tcg_gen_mov_i32(REG(B11_8), addr);
            tcg_temp_free(addr);
        }
@@ -599,7 +608,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_subi_i32(addr, REG(B11_8), 4);
-            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+                                MO_TEUL | UNALIGN(ctx));
            tcg_gen_mov_i32(REG(B11_8), addr);
         tcg_temp_free(addr);
        }
@@ -610,12 +620,14 @@ static void _decode_opc(DisasContext * ctx)
                tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
        return;
     case 0x6005:               /* mov.w @Rm+,Rn */
-        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
+        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+                            MO_TESW | UNALIGN(ctx));
        if ( B11_8 != B7_4 )
                tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
        return;
     case 0x6006:               /* mov.l @Rm+,Rn */
-        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
+        tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx,
+                            MO_TESL | UNALIGN(ctx));
        if ( B11_8 != B7_4 )
                tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
        return;
@@ -631,7 +643,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_add_i32(addr, REG(B11_8), REG(0));
-            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
+            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+                                MO_TEUW | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
@@ -639,7 +652,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_add_i32(addr, REG(B11_8), REG(0));
-            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
+            tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx,
+                                MO_TEUL | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
@@ -655,7 +669,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_add_i32(addr, REG(B7_4), REG(0));
-            tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
+            tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+                                MO_TESW | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
@@ -663,7 +678,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_add_i32(addr, REG(B7_4), REG(0));
-            tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
+            tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
+                                MO_TESL | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
@@ -1257,7 +1273,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
-            tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
+            tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx,
+                                MO_TEUW | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
@@ -1273,7 +1290,8 @@ static void _decode_opc(DisasContext * ctx)
        {
            TCGv addr = tcg_temp_new();
            tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
-            tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
+            tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx,
+                                MO_TESW | UNALIGN(ctx));
            tcg_temp_free(addr);
        }
        return;
-- 
2.25.1

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[PATCH v2 46/55] linux-user: Disable more prctl subcodes, (continued)
- [PATCH v2 46/55] linux-user: Disable more prctl subcodes, Richard Henderson, 2021/08/03
- [PATCH v2 47/55] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass, Richard Henderson, 2021/08/03
- [PATCH v2 45/55] linux-user: Split out do_prctl and subroutines, Richard Henderson, 2021/08/03
- [PATCH v2 48/55] linux-user: Add code for PR_GET/SET_UNALIGN, Richard Henderson, 2021/08/03
- [PATCH v2 49/55] hw/core/cpu: Move cpu properties to cpu-sysemu.c, Richard Henderson, 2021/08/03
- [PATCH v2 50/55] hw/core/cpu: Add prctl-unalign-sigbus property for user-only, Richard Henderson, 2021/08/03
- [PATCH v2 51/55] target/alpha: Reorg fp memory operations, Richard Henderson, 2021/08/03
- [PATCH v2 52/55] target/alpha: Reorg integer memory operations, Richard Henderson, 2021/08/03
- [PATCH v2 53/55] target/alpha: Implement prctl_unalign_sigbus, Richard Henderson, 2021/08/03
- [PATCH v2 54/55] target/hppa: Implement prctl_unalign_sigbus, Richard Henderson, 2021/08/03
- [PATCH v2 55/55] target/sh4: Implement prctl_unalign_sigbus, Richard Henderson <=

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