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[PATCH for-6.2 24/53] target/arm: Rename MVEGenDualAccOpFn to MVEGenLong
From: |
Peter Maydell |
Subject: |
[PATCH for-6.2 24/53] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn |
Date: |
Thu, 29 Jul 2021 12:14:43 +0100 |
The MVEGenDualAccOpFn is a bit misnamed, since it is used for
the "long dual accumulate" operations that use a 64-bit
accumulator. Rename it to MVEGenLongDualAccOpFn so we can
use the former name for the 32-bit accumulator insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-mve.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 5c3655efc3c..676411e05cb 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -38,7 +38,7 @@ typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void MVEGenTwoOpShiftFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32);
-typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr,
TCGv_i64);
+typedef void MVEGenLongDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr,
TCGv_i64);
typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void MVEGenOneOpImmFn(TCGv_ptr, TCGv_ptr, TCGv_i64);
typedef void MVEGenVIDUPFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32, TCGv_i32);
@@ -652,7 +652,7 @@ static bool trans_VQDMULLT_scalar(DisasContext *s,
arg_2scalar *a)
}
static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
- MVEGenDualAccOpFn *fn)
+ MVEGenLongDualAccOpFn *fn)
{
TCGv_ptr qn, qm;
TCGv_i64 rda;
@@ -710,7 +710,7 @@ static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav
*a,
static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a)
{
- static MVEGenDualAccOpFn * const fns[4][2] = {
+ static MVEGenLongDualAccOpFn * const fns[4][2] = {
{ NULL, NULL },
{ gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh },
{ gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw },
@@ -721,7 +721,7 @@ static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav
*a)
static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a)
{
- static MVEGenDualAccOpFn * const fns[4][2] = {
+ static MVEGenLongDualAccOpFn * const fns[4][2] = {
{ NULL, NULL },
{ gen_helper_mve_vmlaldavuh, NULL },
{ gen_helper_mve_vmlaldavuw, NULL },
@@ -732,7 +732,7 @@ static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav
*a)
static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a)
{
- static MVEGenDualAccOpFn * const fns[4][2] = {
+ static MVEGenLongDualAccOpFn * const fns[4][2] = {
{ NULL, NULL },
{ gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh },
{ gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw },
@@ -743,7 +743,7 @@ static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a)
static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a)
{
- static MVEGenDualAccOpFn * const fns[] = {
+ static MVEGenLongDualAccOpFn * const fns[] = {
gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw,
};
return do_long_dual_acc(s, a, fns[a->x]);
@@ -751,7 +751,7 @@ static bool trans_VRMLALDAVH_S(DisasContext *s,
arg_vmlaldav *a)
static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a)
{
- static MVEGenDualAccOpFn * const fns[] = {
+ static MVEGenLongDualAccOpFn * const fns[] = {
gen_helper_mve_vrmlaldavhuw, NULL,
};
return do_long_dual_acc(s, a, fns[a->x]);
@@ -759,7 +759,7 @@ static bool trans_VRMLALDAVH_U(DisasContext *s,
arg_vmlaldav *a)
static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a)
{
- static MVEGenDualAccOpFn * const fns[] = {
+ static MVEGenLongDualAccOpFn * const fns[] = {
gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw,
};
return do_long_dual_acc(s, a, fns[a->x]);
--
2.20.1
- [PATCH for-6.2 26/53] target/arm: Implement MVE VMLA, (continued)
- [PATCH for-6.2 26/53] target/arm: Implement MVE VMLA, Peter Maydell, 2021/07/29
- [PATCH for-6.2 36/53] target/arm: Implement MVE VADD (floating-point), Peter Maydell, 2021/07/29
- [PATCH for-6.2 39/53] target/arm: Implement MVE VFMA and VFMS, Peter Maydell, 2021/07/29
- [PATCH for-6.2 19/53] target/arm: Implement MVE shift-by-scalar, Peter Maydell, 2021/07/29
- [PATCH for-6.2 22/53] target/arm: Implement MVE VABAV, Peter Maydell, 2021/07/29
- [PATCH for-6.2 24/53] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn,
Peter Maydell <=
- [PATCH for-6.2 32/53] target/arm: Implement MVE VCTP, Peter Maydell, 2021/07/29
- [PATCH for-6.2 31/53] target/arm: Implement MVE VPNOT, Peter Maydell, 2021/07/29
- [PATCH for-6.2 34/53] target/arm: Implement MVE scatter-gather immediate forms, Peter Maydell, 2021/07/29
- [PATCH for-6.2 41/53] target/arm: Implement MVE VMAXNMA and VMINNMA, Peter Maydell, 2021/07/29
- [PATCH for-6.2 52/53] target/arm: Implement MVE VRINT insns, Peter Maydell, 2021/07/29
- [PATCH for-6.2 45/53] target/arm: Implement MVE FP max/min across vector, Peter Maydell, 2021/07/29
- [PATCH for-6.2 25/53] target/arm: Implement MVE VMLADAV and VMLSLDAV, Peter Maydell, 2021/07/29