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Re: [PATCH v6 1/5] hw/nvme: split pmrmsc register into upper and lower
From: |
Keith Busch |
Subject: |
Re: [PATCH v6 1/5] hw/nvme: split pmrmsc register into upper and lower |
Date: |
Mon, 26 Jul 2021 08:25:27 -0700 |
On Wed, Jul 21, 2021 at 09:48:32AM +0200, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to
> make up the 64 bit logical PMRMSC register.
>
> Make it so.
Looks good.
Reviewed-by: Keith Busch <kbusch@kernel.org>
- [PATCH v6 0/5] hw/nvme: fix mmio read, Klaus Jensen, 2021/07/21
- [PATCH v6 1/5] hw/nvme: split pmrmsc register into upper and lower, Klaus Jensen, 2021/07/21
- [PATCH v6 2/5] hw/nvme: use symbolic names for registers, Klaus Jensen, 2021/07/21
- [PATCH v6 3/5] hw/nvme: fix out-of-bounds reads, Klaus Jensen, 2021/07/21
- [PATCH v6 5/5] tests/qtest/nvme-test: add mmio read test, Klaus Jensen, 2021/07/21
- [PATCH v6 4/5] hw/nvme: fix mmio read, Klaus Jensen, 2021/07/21