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From: | Sebastian Huber |
Subject: | Re: [PATCH] hw/intc/arm_gic: Fix set/clear pending of PPI/SPI |
Date: | Fri, 23 Jul 2021 16:04:12 +0200 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.0 |
On 09/07/2021 11:49, Sebastian Huber wrote:
According to the GICv3 specification register GICD_ISPENDR0 is Banked for each connected PE with GICR_TYPER.Processor_Number < 8. For Qemu this is the case since GIC_NCPU == 8. For SPI, make the interrupt pending on all CPUs and not just the processor targets of the interrupt. This behaviour is at least present on the i.MX7D which uses an Cortex-A7MPCore.
Could someone please have a look at this patch? -- embedded brains GmbH Herr Sebastian HUBER Dornierstr. 4 82178 Puchheim Germany email: sebastian.huber@embedded-brains.de phone: +49-89-18 94 741 - 16 fax: +49-89-18 94 741 - 08 Registergericht: Amtsgericht München Registernummer: HRB 157899 Vertretungsberechtigte Geschäftsführer: Peter Rasmussen, Thomas Dörfler Unsere Datenschutzerklärung finden Sie hier: https://embedded-brains.de/datenschutzerklaerung/
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