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[PULL 13/27] target/alpha: Drop goto_tb path in gen_call_pal
From: |
Richard Henderson |
Subject: |
[PULL 13/27] target/alpha: Drop goto_tb path in gen_call_pal |
Date: |
Wed, 21 Jul 2021 09:59:40 -1000 |
We are certain of a page crossing here, entering the
PALcode image, so the call to use_goto_tb that should
have been here will never succeed.
We are shortly going to add an assert to tcg_gen_goto_tb
that would trigger for this case.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/translate.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 103c6326a2..949ba6ffde 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -1207,19 +1207,8 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int
palcode)
? 0x2000 + (palcode - 0x80) * 64
: 0x1000 + palcode * 64);
- /* Since the destination is running in PALmode, we don't really
- need the page permissions check. We'll see the existence of
- the page when we create the TB, and we'll flush all TBs if
- we change the PAL base register. */
- if (!ctx->base.singlestep_enabled) {
- tcg_gen_goto_tb(0);
- tcg_gen_movi_i64(cpu_pc, entry);
- tcg_gen_exit_tb(ctx->base.tb, 0);
- return DISAS_NORETURN;
- } else {
- tcg_gen_movi_i64(cpu_pc, entry);
- return DISAS_PC_UPDATED;
- }
+ tcg_gen_movi_i64(cpu_pc, entry);
+ return DISAS_PC_UPDATED;
}
#endif
}
--
2.25.1
- [PULL 03/27] qemu/atomic: Add aligned_{int64,uint64}_t types, (continued)
- [PULL 03/27] qemu/atomic: Add aligned_{int64,uint64}_t types, Richard Henderson, 2021/07/21
- [PULL 04/27] tcg: Rename helper_atomic_*_mmu and provide for user-only, Richard Henderson, 2021/07/21
- [PULL 05/27] accel/tcg: Standardize atomic helpers on softmmu api, Richard Henderson, 2021/07/21
- [PULL 06/27] accel/tcg: Fold EXTRA_ARGS into atomic_template.h, Richard Henderson, 2021/07/21
- [PULL 07/27] accel/tcg: Remove ATOMIC_MMU_DECLS, Richard Henderson, 2021/07/21
- [PULL 08/27] accel/tcg: Expand ATOMIC_MMU_LOOKUP_*, Richard Henderson, 2021/07/21
- [PULL 09/27] trace: Fold mem-internal.h into mem.h, Richard Henderson, 2021/07/21
- [PULL 10/27] accel/tcg: Push trace info building into atomic_common.c.inc, Richard Henderson, 2021/07/21
- [PULL 11/27] accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS, Richard Henderson, 2021/07/21
- [PULL 12/27] accel/tcg: Move curr_cflags into cpu-exec.c, Richard Henderson, 2021/07/21
- [PULL 13/27] target/alpha: Drop goto_tb path in gen_call_pal,
Richard Henderson <=
- [PULL 14/27] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR, Richard Henderson, 2021/07/21
- [PULL 20/27] target/i386: Implement debug_check_breakpoint, Richard Henderson, 2021/07/21
- [PULL 17/27] accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic, Richard Henderson, 2021/07/21
- [PULL 26/27] accel/tcg: Hoist tb_cflags to a local in translator_loop, Richard Henderson, 2021/07/21
- [PULL 22/27] target/avr: Implement gdb_adjust_breakpoint, Richard Henderson, 2021/07/21
- [PULL 19/27] target/arm: Implement debug_check_breakpoint, Richard Henderson, 2021/07/21
- [PULL 21/27] hw/core: Introduce CPUClass.gdb_adjust_breakpoint, Richard Henderson, 2021/07/21
- [PULL 24/27] accel/tcg: Move breakpoint recognition outside translation, Richard Henderson, 2021/07/21
- [PULL 25/27] accel/tcg: Remove TranslatorOps.breakpoint_check, Richard Henderson, 2021/07/21
- [PULL 27/27] accel/tcg: Record singlestep_enabled in tb->cflags, Richard Henderson, 2021/07/21