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Re: [PULL v2 00/12] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL v2 00/12] riscv-to-apply queue |
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Date: |
Fri, 16 Jul 2021 10:55:20 +0100 |
On Thu, 15 Jul 2021 at 08:16, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit a9649a719a44894b81f38dc1c5c1888ee684acef:
>
> Merge remote-tracking branch
> 'remotes/cleber-gitlab/tags/python-next-pull-request' into staging
> (2021-07-14 18:09:09 +0100)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210715
>
> for you to fetch changes up to b3d8aa20692b1baed299790f4a65d6b0cfb1a0bc:
>
> hw/riscv/boot: Check the error of fdt_pack() (2021-07-15 09:35:46 +1000)
>
> ----------------------------------------------------------------
> Fourth RISC-V PR for 6.1 release
>
> - Code cleanups
> - Documentation improvements
> - Hypervisor extension improvements with hideleg and hedeleg
> - sifive_u fixes
> - OpenTitan register layout updates
> - Fix coverity issue
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
- [PULL v2 03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc, (continued)
- [PULL v2 03/12] docs/system: riscv: Fix CLINT name in the sifive_u doc, Alistair Francis, 2021/07/15
- [PULL v2 04/12] docs/system: riscv: Add documentation for virt machine, Alistair Francis, 2021/07/15
- [PULL v2 05/12] target/riscv: hardwire bits in hideleg and hedeleg, Alistair Francis, 2021/07/15
- [PULL v2 06/12] docs/system: riscv: Update Microchip Icicle Kit for direct kernel boot, Alistair Francis, 2021/07/15
- [PULL v2 07/12] hw/riscv: sifive_u: Correct the CLINT timebase frequency, Alistair Francis, 2021/07/15
- [PULL v2 08/12] hw/riscv: sifive_u: Make sure firmware info is 8-byte aligned, Alistair Francis, 2021/07/15
- [PULL v2 09/12] char: ibex_uart: Update the register layout, Alistair Francis, 2021/07/15
- [PULL v2 11/12] hw/riscv: opentitan: Add the flash alias, Alistair Francis, 2021/07/15
- [PULL v2 10/12] hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri, Alistair Francis, 2021/07/15
- [PULL v2 12/12] hw/riscv/boot: Check the error of fdt_pack(), Alistair Francis, 2021/07/15
- Re: [PULL v2 00/12] riscv-to-apply queue,
Peter Maydell <=