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Re: [PATCH v2 1/5] target/riscv: Expose interrupt pending bits as GPIO l
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v2 1/5] target/riscv: Expose interrupt pending bits as GPIO lines |
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Date: |
Thu, 15 Jul 2021 16:21:09 +0800 |
On Wed, Jul 14, 2021 at 3:24 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Expose the 12 interrupt pending bits in MIP as GPIO lines.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
> target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
- [PATCH v2 2/5] hw/intc: sifive_clint: Use RISC-V CPU GPIO lines, (continued)