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[PULL 11/19] target/mips/tx79: Introduce LQ opcode (Load Quadword)
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 11/19] target/mips/tx79: Introduce LQ opcode (Load Quadword) |
Date: |
Sun, 11 Jul 2021 23:00:08 +0200 |
Introduce the LQ opcode (Load Quadword) and remove unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-26-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/tx79.decode | 8 ++++++++
target/mips/tcg/translate.c | 16 ++-------------
target/mips/tcg/tx79_translate.c | 35 ++++++++++++++++++++++++++++++++
3 files changed, 45 insertions(+), 14 deletions(-)
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode
index 2f65dce2431..0af5c6d0ed1 100644
--- a/target/mips/tcg/tx79.decode
+++ b/target/mips/tcg/tx79.decode
@@ -13,6 +13,8 @@
&rtype rs rt rd sa
+&itype base rt offset
+
###########################################################################
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
@@ -22,6 +24,8 @@
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
+@ldst ...... base:5 rt:5 offset:16 &itype
+
###########################################################################
MFHI1 011100 0000000000 ..... 00000 010000 @rd
@@ -62,3 +66,7 @@ PCPYUD 011100 ..... ..... ..... 01110 101001
@rs_rt_rd
POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
+
+# SPECIAL
+
+LQ 011110 ..... ..... ................ @ldst
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index ae33c75f088..82a7f2bcc63 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1180,7 +1180,6 @@ enum {
enum {
MMI_OPC_CLASS_MMI = 0x1C << 26, /* Same as OPC_SPECIAL2 */
- MMI_OPC_LQ = 0x1E << 26, /* Same as OPC_MSA */
MMI_OPC_SQ = 0x1F << 26, /* Same as OPC_SPECIAL3 */
};
@@ -15179,11 +15178,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext
*ctx)
}
}
-static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
-{
- gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
-}
-
static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
@@ -16082,14 +16076,8 @@ static bool decode_opc_legacy(CPUMIPSState *env,
DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
- case OPC_MDMX: /* MMI_OPC_LQ */
- if (ctx->insn_flags & INSN_R5900) {
-#if defined(TARGET_MIPS64)
- gen_mmi_lq(env, ctx);
-#endif
- } else {
- /* MDMX: Not implemented. */
- }
+ case OPC_MDMX:
+ /* MDMX: Not implemented. */
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS_R6);
diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c
index 402790249f3..d9193b4d86e 100644
--- a/target/mips/tcg/tx79_translate.c
+++ b/target/mips/tcg/tx79_translate.c
@@ -334,6 +334,41 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a)
* SQ rt, offset(base) Store Quadword
*/
+static bool trans_LQ(DisasContext *ctx, arg_itype *a)
+{
+ TCGv_i64 t0;
+ TCGv addr;
+
+ if (a->rt == 0) {
+ /* nop */
+ return true;
+ }
+
+ t0 = tcg_temp_new_i64();
+ addr = tcg_temp_new();
+
+ gen_base_offset_addr(ctx, addr, a->base, a->offset);
+ /*
+ * Clear least-significant four bits of the effective
+ * address, effectively creating an aligned address.
+ */
+ tcg_gen_andi_tl(addr, addr, ~0xf);
+
+ /* Lower half */
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+ gen_store_gpr(t0, a->rt);
+
+ /* Upper half */
+ tcg_gen_addi_i64(addr, addr, 8);
+ tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, MO_TEQ);
+ gen_store_gpr_hi(t0, a->rt);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(addr);
+
+ return true;
+}
+
/*
* Multiply and Divide (19 instructions)
* -------------------------------------
--
2.31.1
- [PULL 01/19] hw/pci-host: Rename Raven ASIC PCI bridge as raven.c, (continued)
- [PULL 01/19] hw/pci-host: Rename Raven ASIC PCI bridge as raven.c, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 03/19] target/mips/tx79: Introduce PAND/POR/PXOR/PNOR opcodes (parallel logic), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 04/19] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 02/19] hw/pci-host/raven: Add PCI_IO_BASE_ADDR definition, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 05/19] target/mips/tx79: Introduce PEXTUW (Parallel Extend Upper from Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 06/19] target/mips/tx79: Introduce PEXTL[BHW] opcodes (Parallel Extend Lower), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 07/19] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 08/19] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 09/19] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 10/19] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 11/19] target/mips/tx79: Introduce LQ opcode (Load Quadword),
Philippe Mathieu-Daudé <=
- [PULL 12/19] target/mips/tx79: Introduce SQ opcode (Store Quadword), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 13/19] target/mips: Rewrite UHI errno_mips() using switch statement, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 14/19] dp8393x: fix CAM descriptor entry index, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 15/19] dp8393x: Replace address_space_rw(is_write=1) by address_space_write(), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 16/19] dp8393x: Replace 0x40 magic value by SONIC_REG_COUNT definition, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 17/19] dp8393x: Store CAM registers as 16-bit, Philippe Mathieu-Daudé, 2021/07/11
- [PULL 18/19] dp8393x: Rewrite dp8393x_get() / dp8393x_put(), Philippe Mathieu-Daudé, 2021/07/11
- [PULL 19/19] dp8393x: don't force 32-bit register access, Philippe Mathieu-Daudé, 2021/07/11
- Re: [PULL 00/19] MIPS patches for 2021-07-11, Philippe Mathieu-Daudé, 2021/07/11