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Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO l
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines |
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Date: |
Sat, 10 Jul 2021 22:40:46 +0800 |
On Fri, Jul 9, 2021 at 11:30 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Expose the 12 interrupt pending bits in MIP as GPIO lines.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
- Re: [PATCH v1 3/5] hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines, (continued)