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[PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints
From: |
Peter Maydell |
Subject: |
[PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints |
Date: |
Fri, 9 Jul 2021 17:09:52 +0100 |
Convert the use of the DPRINTF debug macro in the PL061 model to
use tracepoints.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/gpio/pl061.c | 27 +++++++++------------------
hw/gpio/trace-events | 6 ++++++
2 files changed, 15 insertions(+), 18 deletions(-)
diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c
index e72e77572a0..a6ace88895d 100644
--- a/hw/gpio/pl061.c
+++ b/hw/gpio/pl061.c
@@ -15,19 +15,7 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "qom/object.h"
-
-//#define DEBUG_PL061 1
-
-#ifdef DEBUG_PL061
-#define DPRINTF(fmt, ...) \
-do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} while
(0)
-#else
-#define DPRINTF(fmt, ...) do {} while(0)
-#define BADF(fmt, ...) \
-do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0)
-#endif
+#include "trace.h"
static const uint8_t pl061_id[12] =
{ 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
@@ -107,7 +95,7 @@ static void pl061_update(PL061State *s)
uint8_t out;
int i;
- DPRINTF("dir = %d, data = %d\n", s->dir, s->data);
+ trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data);
/* Outputs float high. */
/* FIXME: This is board dependent. */
@@ -118,8 +106,9 @@ static void pl061_update(PL061State *s)
for (i = 0; i < N_GPIOS; i++) {
mask = 1 << i;
if (changed & mask) {
- DPRINTF("Set output %d = %d\n", i, (out & mask) != 0);
- qemu_set_irq(s->out[i], (out & mask) != 0);
+ int level = (out & mask) != 0;
+ trace_pl061_set_output(DEVICE(s)->canonical_path, i, level);
+ qemu_set_irq(s->out[i], level);
}
}
}
@@ -131,7 +120,8 @@ static void pl061_update(PL061State *s)
for (i = 0; i < N_GPIOS; i++) {
mask = 1 << i;
if (changed & mask) {
- DPRINTF("Changed input %d = %d\n", i, (s->data & mask) != 0);
+ trace_pl061_input_change(DEVICE(s)->canonical_path, i,
+ (s->data & mask) != 0);
if (!(s->isense & mask)) {
/* Edge interrupt */
@@ -150,7 +140,8 @@ static void pl061_update(PL061State *s)
/* Level interrupt */
s->istate |= ~(s->data ^ s->iev) & s->isense;
- DPRINTF("istate = %02X\n", s->istate);
+ trace_pl061_update_istate(DEVICE(s)->canonical_path,
+ s->istate, s->im, (s->istate & s->im) != 0);
qemu_set_irq(s->irq, (s->istate & s->im) != 0);
}
diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events
index f0b664158e2..48ccbb183cc 100644
--- a/hw/gpio/trace-events
+++ b/hw/gpio/trace-events
@@ -13,6 +13,12 @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offset
0x%" PRIx64 " value 0x
nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRIi64
nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 "
value %" PRIi64
+# pl061.c
+pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x
GPIODATA 0x%x"
+pl061_set_output(const char *id, int gpio, int level) "%s setting output %d to
%d"
+pl061_input_change(const char *id, int gpio, int level) "%s input %d changed
to %d"
+pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int level)
"%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d"
+
# sifive_gpio.c
sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value 0x%"
PRIx64
sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " value
0x%" PRIx64
--
2.20.1
- [PULL 00/17] target-arm queue, Peter Maydell, 2021/07/09
- [PULL 01/17] stm32f100: Add the stm32f100 SoC, Peter Maydell, 2021/07/09
- [PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine, Peter Maydell, 2021/07/09
- [PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write, Peter Maydell, 2021/07/09
- [PULL 03/17] docs/system: arm: Add stm32 boards description, Peter Maydell, 2021/07/09
- [PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase, Peter Maydell, 2021/07/09
- [PULL 09/17] hw/gpio/pl061: Document the interface of this device, Peter Maydell, 2021/07/09
- [PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic, Peter Maydell, 2021/07/09
- [PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints,
Peter Maydell <=
- [PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write, Peter Maydell, 2021/07/09
- [PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset, Peter Maydell, 2021/07/09
- [PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect, Peter Maydell, 2021/07/09
- [PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message, Peter Maydell, 2021/07/09
- [PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers, Peter Maydell, 2021/07/09
- [PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint, Peter Maydell, 2021/07/09
- [PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable, Peter Maydell, 2021/07/09
- [PULL 14/17] hw/gpio/pl061: Document a shortcoming in our implementation, Peter Maydell, 2021/07/09
- [PULL 12/17] hw/arm/virt: Make PL061 GPIO lines pulled low, not high, Peter Maydell, 2021/07/09
- Re: [PULL 00/17] target-arm queue, Peter Maydell, 2021/07/11