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[PATCH v5 1/9] hw/pci/pci_host: Allow PCI host to bypass iommu
From: |
Wang Xingang |
Subject: |
[PATCH v5 1/9] hw/pci/pci_host: Allow PCI host to bypass iommu |
Date: |
Thu, 8 Jul 2021 12:55:11 +0000 |
From: Xingang Wang <wangxingang5@huawei.com>
Add a new bypass_iommu property for PCI host and use it to check
whether devices attached to the PCI root bus will bypass iommu.
In pci_device_iommu_address_space(), check the property and
avoid getting iommu address space for devices bypass iommu.
Signed-off-by: Xingang Wang <wangxingang5@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
---
hw/pci/pci.c | 18 +++++++++++++++++-
hw/pci/pci_host.c | 1 +
include/hw/pci/pci.h | 1 +
include/hw/pci/pci_host.h | 1 +
4 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 377084f1a8..27d588e268 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -416,6 +416,22 @@ const char *pci_root_bus_path(PCIDevice *dev)
return rootbus->qbus.name;
}
+bool pci_bus_bypass_iommu(PCIBus *bus)
+{
+ PCIBus *rootbus = bus;
+ PCIHostState *host_bridge;
+
+ if (!pci_bus_is_root(bus)) {
+ rootbus = pci_device_root_bus(bus->parent_dev);
+ }
+
+ host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent);
+
+ assert(host_bridge->bus == rootbus);
+
+ return host_bridge->bypass_iommu;
+}
+
static void pci_root_bus_init(PCIBus *bus, DeviceState *parent,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
@@ -2718,7 +2734,7 @@ AddressSpace *pci_device_iommu_address_space(PCIDevice
*dev)
iommu_bus = parent_bus;
}
- if (iommu_bus && iommu_bus->iommu_fn) {
+ if (!pci_bus_bypass_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) {
return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn);
}
return &address_space_memory;
diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
index 8ca5fadcbd..cf02f0d6a5 100644
--- a/hw/pci/pci_host.c
+++ b/hw/pci/pci_host.c
@@ -222,6 +222,7 @@ const VMStateDescription vmstate_pcihost = {
static Property pci_host_properties_common[] = {
DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState,
mig_enabled, true),
+ DEFINE_PROP_BOOL("bypass-iommu", PCIHostState, bypass_iommu, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 6be4e0c460..f4d51b672b 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -480,6 +480,7 @@ void pci_for_each_bus(PCIBus *bus,
PCIBus *pci_device_root_bus(const PCIDevice *d);
const char *pci_root_bus_path(PCIDevice *dev);
+bool pci_bus_bypass_iommu(PCIBus *bus);
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
int pci_qdev_find_device(const char *id, PCIDevice **pdev);
void pci_bus_get_w64_range(PCIBus *bus, Range *range);
diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h
index 52e038c019..c6f4eb4585 100644
--- a/include/hw/pci/pci_host.h
+++ b/include/hw/pci/pci_host.h
@@ -43,6 +43,7 @@ struct PCIHostState {
uint32_t config_reg;
bool mig_enabled;
PCIBus *bus;
+ bool bypass_iommu;
QLIST_ENTRY(PCIHostState) next;
};
--
2.19.1
- [PATCH v5 0/9] IOMMU: Add support for IOMMU Bypass Feature, Wang Xingang, 2021/07/08
- [PATCH v5 7/9] hw/i386/acpi-build: Add DMAR support to bypass iommu, Wang Xingang, 2021/07/08
- [PATCH v5 2/9] hw/pxb: Add a bypass iommu property, Wang Xingang, 2021/07/08
- [PATCH v5 8/9] hw/i386/acpi-build: Add IVRS support to bypass iommu, Wang Xingang, 2021/07/08
- [PATCH v5 6/9] hw/arm/virt-acpi-build: Add IORT support to bypass SMMUv3, Wang Xingang, 2021/07/08
- [PATCH v5 9/9] docs: Add documentation for iommu bypass, Wang Xingang, 2021/07/08
- [PATCH v5 5/9] hw/pci: Add pci_bus_range() to get PCI bus number range, Wang Xingang, 2021/07/08
- [PATCH v5 1/9] hw/pci/pci_host: Allow PCI host to bypass iommu,
Wang Xingang <=
- [PATCH v5 3/9] hw/arm/virt: Add default_bus_bypass_iommu machine option, Wang Xingang, 2021/07/08
- [PATCH v5 4/9] hw/i386: Add a default_bus_bypass_iommu pc machine option, Wang Xingang, 2021/07/08