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[PULL 47/63] tcg/s390: Support bswap flags
From: |
Richard Henderson |
Subject: |
[PULL 47/63] tcg/s390: Support bswap flags |
Date: |
Tue, 29 Jun 2021 11:54:39 -0700 |
For INDEX_op_bswap16_i64, use 64-bit instructions so that we can
easily provide the extension to 64-bits. Drop the special case,
previously used, where the input is already zero-extended -- the
minor code size savings is not worth the complication.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 5fe073f09a..b82cf19f09 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -1951,15 +1951,37 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tgen_ext16u(s, TCG_TYPE_I32, args[0], args[1]);
break;
- OP_32_64(bswap16):
- /* The TCG bswap definition requires bits 0-47 already be zero.
- Thus we don't need the G-type insns to implement bswap16_i64. */
- tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
- tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
+ case INDEX_op_bswap16_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_sh32(s, RS_SRA, a0, TCG_REG_NONE, 16);
+ } else {
+ tcg_out_sh32(s, RS_SRL, a0, TCG_REG_NONE, 16);
+ }
break;
- OP_32_64(bswap32):
+ case INDEX_op_bswap16_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVGR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tcg_out_sh64(s, RSY_SRAG, a0, a0, TCG_REG_NONE, 48);
+ } else {
+ tcg_out_sh64(s, RSY_SRLG, a0, a0, TCG_REG_NONE, 48);
+ }
+ break;
+
+ case INDEX_op_bswap32_i32:
tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
break;
+ case INDEX_op_bswap32_i64:
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ tcg_out_insn(s, RRE, LRVR, a0, a1);
+ if (a2 & TCG_BSWAP_OS) {
+ tgen_ext32s(s, a0, a0);
+ } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tgen_ext32u(s, a0, a0);
+ }
+ break;
case INDEX_op_add2_i32:
if (const_args[4]) {
--
2.25.1
- [PULL 39/63] tcg/arm: Support bswap flags, (continued)
- [PULL 39/63] tcg/arm: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 33/63] tcg: Implement tcg_gen_vec_add{sub}32_tl, Richard Henderson, 2021/06/29
- [PULL 37/63] tcg/aarch64: Merge tcg_out_rev{16,32,64}, Richard Henderson, 2021/06/29
- [PULL 40/63] tcg/ppc: Split out tcg_out_ext{8,16,32}s, Richard Henderson, 2021/06/29
- [PULL 41/63] tcg/ppc: Split out tcg_out_sari{32,64}, Richard Henderson, 2021/06/29
- [PULL 45/63] tcg/ppc: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 42/63] tcg/ppc: Split out tcg_out_bswap16, Richard Henderson, 2021/06/29
- [PULL 43/63] tcg/ppc: Split out tcg_out_bswap32, Richard Henderson, 2021/06/29
- [PULL 44/63] tcg/ppc: Split out tcg_out_bswap64, Richard Henderson, 2021/06/29
- [PULL 48/63] tcg/mips: Support bswap flags in tcg_out_bswap16, Richard Henderson, 2021/06/29
- [PULL 47/63] tcg/s390: Support bswap flags,
Richard Henderson <=
- [PULL 49/63] tcg/mips: Support bswap flags in tcg_out_bswap32, Richard Henderson, 2021/06/29
- [PULL 46/63] tcg/ppc: Use power10 byte-reverse instructions, Richard Henderson, 2021/06/29
- [PULL 52/63] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64, Richard Henderson, 2021/06/29
- [PULL 51/63] tcg: Handle new bswap flags during optimize, Richard Henderson, 2021/06/29
- [PULL 54/63] tcg: Make use of bswap flags in tcg_gen_qemu_st_*, Richard Henderson, 2021/06/29
- [PULL 50/63] tcg/tci: Support bswap flags, Richard Henderson, 2021/06/29
- [PULL 53/63] tcg: Make use of bswap flags in tcg_gen_qemu_ld_*, Richard Henderson, 2021/06/29
- [PULL 57/63] target/arm: Improve REVSH, Richard Henderson, 2021/06/29
- [PULL 59/63] target/sh4: Improve swap.b translation, Richard Henderson, 2021/06/29
- [PULL 56/63] target/arm: Improve vector REV, Richard Henderson, 2021/06/29