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[PULL 29/63] tcg: Add tcg_gen_vec_add{sub}16_i32
From: |
Richard Henderson |
Subject: |
[PULL 29/63] tcg: Add tcg_gen_vec_add{sub}16_i32 |
Date: |
Tue, 29 Jun 2021 11:54:21 -0700 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Implement tcg_gen_vec_add{sub}16_tl by adding corresponding i32 OP.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20210624105023.3852-2-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-gvec.h | 13 +++++++++++++
tcg/tcg-op-gvec.c | 28 ++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index c69a7de984..9b67822f54 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -401,4 +401,17 @@ void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a,
int64_t);
void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c);
+/* 32-bit vector operations. */
+void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
+
+void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
+
+#if TARGET_LONG_BITS == 64
+#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64
+#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i64
+#else
+#define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32
+#define tcg_gen_vec_sub16_tl tcg_gen_vec_sub16_i32
+#endif
+
#endif
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 515db120cc..7ddd56c0e6 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -1742,6 +1742,20 @@ void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a,
TCGv_i64 b)
gen_addv_mask(d, a, b, m);
}
+void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ tcg_gen_andi_i32(t1, a, ~0xffff);
+ tcg_gen_add_i32(t2, a, b);
+ tcg_gen_add_i32(t1, t1, b);
+ tcg_gen_deposit_i32(d, t1, t2, 0, 16);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -1892,6 +1906,20 @@ void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a,
TCGv_i64 b)
gen_subv_mask(d, a, b, m);
}
+void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ tcg_gen_andi_i32(t1, b, ~0xffff);
+ tcg_gen_sub_i32(t2, a, b);
+ tcg_gen_sub_i32(t1, a, t1);
+ tcg_gen_deposit_i32(d, t1, t2, 0, 16);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
TCGv_i64 t1 = tcg_temp_new_i64();
--
2.25.1
- [PULL 02/63] target/nios2: Use global cpu_env, (continued)
- [PULL 02/63] target/nios2: Use global cpu_env, Richard Henderson, 2021/06/29
- [PULL 03/63] target/nios2: Use global cpu_R, Richard Henderson, 2021/06/29
- [PULL 06/63] target/nios2: Remove assignment to env in handle_instruction, Richard Henderson, 2021/06/29
- [PULL 04/63] target/nios2: Add DisasContextBase to DisasContext, Richard Henderson, 2021/06/29
- [PULL 05/63] target/nios2: Convert to TranslatorOps, Richard Henderson, 2021/06/29
- [PULL 07/63] target/nios2: Clean up goto in handle_instruction, Richard Henderson, 2021/06/29
- [PULL 08/63] target/nios2: Inline handle_instruction, Richard Henderson, 2021/06/29
- [PULL 12/63] target/avr: Convert to TranslatorOps, Richard Henderson, 2021/06/29
- [PULL 09/63] target/nios2: Use pc_next for pc + 4, Richard Henderson, 2021/06/29
- [PULL 17/63] target/cris: Fix use_goto_tb, Richard Henderson, 2021/06/29
- [PULL 29/63] tcg: Add tcg_gen_vec_add{sub}16_i32,
Richard Henderson <=
- [PULL 22/63] target/cris: Set cpustate_changed for rfe/rfn, Richard Henderson, 2021/06/29
- [PULL 19/63] target/cris: Mark helper_raise_exception noreturn, Richard Henderson, 2021/06/29
- [PULL 15/63] target/cris: Replace DISAS_TB_JUMP with DISAS_NORETURN, Richard Henderson, 2021/06/29
- [PULL 13/63] target/cris: Add DisasContextBase to DisasContext, Richard Henderson, 2021/06/29
- [PULL 18/63] target/cris: Convert to TranslatorOps, Richard Henderson, 2021/06/29
- [PULL 11/63] target/avr: Change ctx to DisasContext* in gen_intermediate_code, Richard Henderson, 2021/06/29
- [PULL 20/63] target/cris: Mark static arrays const, Richard Henderson, 2021/06/29
- [PULL 27/63] target/cris: Remove dc->flagx_known, Richard Henderson, 2021/06/29
- [PULL 26/63] target/cris: Improve JMP_INDIRECT, Richard Henderson, 2021/06/29
- [PULL 23/63] target/cris: Add DISAS_UPDATE_NEXT, Richard Henderson, 2021/06/29