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[PATCH 00/18] target/arm: Second slice of MVE implementation
From: |
Peter Maydell |
Subject: |
[PATCH 00/18] target/arm: Second slice of MVE implementation |
Date: |
Mon, 28 Jun 2021 14:58:17 +0100 |
This patchseries provides the second slice of the MVE implementation.
In this series:
* fixes for bugs in a couple of the insns committed to upstream
as part of the first slice
* the logical immediate insns (including a preliminary refactoring
to share the asimd_imm_const() decode between Neon, A64 and MVE)
* some vector shifts
* all the new MVE shift instructions which sit entirely within the
non-coprocessor part of the encoding space and operate only on
general purpose registers (either 32-bit shifts of one register,
or 64-bit shifts of a register pair). These insns are not
predicable and not subject to beatwise execution.
* VADDLV (add long across vector)
* VSHLC (shift left entire vector with carry in and out)
(I haven't yet got to the shift-vector-by-scalar-in-register
shift insns yet; those will be in some future patchset.)
This is a bit smaller than the first slice patchseries was, but
softfreeze is approaching and I wanted to give this the best chance of
getting through code review before then. (Not that it matters much if
it doesn't, it just means I would be carrying more patches locally
until we reopen for 6.2.)
thanks
-- PMM
Peter Maydell (18):
target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation
target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH
target/arm: Make asimd_imm_const() public
target/arm: Use asimd_imm_const for A64 decode
target/arm: Use dup_const() instead of bitfield_replicate()
target/arm: Implement MVE logical immediate insns
target/arm: Implement MVE vector shift left by immediate insns
target/arm: Implement MVE vector shift right by immediate insns
target/arm: Implement MVE VSHLL
target/arm: Implement MVE VSRI, VSLI
target/arm: Implement MVE VSHRN, VRSHRN
target/arm: Implement MVE saturating narrowing shifts
target/arm: Implement MVE VSHLC
target/arm: Implement MVE VADDLV
target/arm: Implement MVE long shifts by immediate
target/arm: Implement MVE long shifts by register
target/arm: Implement MVE shifts by immediate
target/arm: Implement MVE shifts by register
target/arm/helper-mve.h | 108 ++++++++
target/arm/translate.h | 41 +++
target/arm/mve.decode | 177 +++++++++++-
target/arm/t32.decode | 55 +++-
target/arm/mve_helper.c | 524 ++++++++++++++++++++++++++++++++++--
target/arm/translate-a64.c | 86 +-----
target/arm/translate-mve.c | 261 +++++++++++++++++-
target/arm/translate-neon.c | 81 ------
target/arm/translate.c | 327 +++++++++++++++++++++-
9 files changed, 1465 insertions(+), 195 deletions(-)
--
2.20.1
- [PATCH 00/18] target/arm: Second slice of MVE implementation,
Peter Maydell <=
- [PATCH 02/18] target/arm: Fix bugs in MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/28
- [PATCH 01/18] target/arm: Fix MVE widening/narrowing VLDR/VSTR offset calculation, Peter Maydell, 2021/06/28
- [PATCH 03/18] target/arm: Make asimd_imm_const() public, Peter Maydell, 2021/06/28
- [PATCH 05/18] target/arm: Use dup_const() instead of bitfield_replicate(), Peter Maydell, 2021/06/28
- [PATCH 06/18] target/arm: Implement MVE logical immediate insns, Peter Maydell, 2021/06/28