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[PULL 34/57] target/arm: Implement MVE VSUB, VMUL (scalar)
From: |
Peter Maydell |
Subject: |
[PULL 34/57] target/arm: Implement MVE VSUB, VMUL (scalar) |
Date: |
Mon, 21 Jun 2021 17:28:10 +0100 |
Implement the scalar forms of the MVE VSUB and VMUL insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-24-peter.maydell@linaro.org
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 2 ++
target/arm/mve_helper.c | 2 ++
target/arm/translate-mve.c | 2 ++
4 files changed, 14 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 16b974a4270..912505d0152 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -149,6 +149,14 @@ DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void,
env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vsub_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vsub_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vsub_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_4(mve_vmul_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+DEF_HELPER_FLAGS_4(mve_vmul_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
+
DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 0ee7a727081..af5fba78ce2 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -161,3 +161,5 @@ VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1
0 ... 1 @vmlaldav_no
# Scalar operations
VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar
+VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar
+VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index cb97709fcac..3c62627f2c7 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -512,6 +512,8 @@ DO_2OP_U(vhsubu, do_vhsub_u)
DO_2OP_SCALAR(OP##w, 4, uint32_t, FN)
DO_2OP_SCALAR_U(vadd_scalar, DO_ADD)
+DO_2OP_SCALAR_U(vsub_scalar, DO_SUB)
+DO_2OP_SCALAR_U(vmul_scalar, DO_MUL)
/*
* Multiply add long dual accumulate ops.
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index 388848b4ff0..3c059ad91cd 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -427,6 +427,8 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
}
DO_2OP_SCALAR(VADD_scalar, vadd_scalar)
+DO_2OP_SCALAR(VSUB_scalar, vsub_scalar)
+DO_2OP_SCALAR(VMUL_scalar, vmul_scalar)
static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a,
MVEGenDualAccOpFn *fn)
--
2.20.1
- [PULL 20/57] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, (continued)
- [PULL 20/57] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/21
- [PULL 12/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/21
- [PULL 19/57] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/21
- [PULL 21/57] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/21
- [PULL 26/57] target/arm: Implement MVE VMAX, VMIN, Peter Maydell, 2021/06/21
- [PULL 23/57] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/21
- [PULL 30/57] target/arm: Implement MVE VMLALDAV, Peter Maydell, 2021/06/21
- [PULL 25/57] target/arm: Implement MVE VRMULH, Peter Maydell, 2021/06/21
- [PULL 37/57] target/arm: Implement MVE VPST, Peter Maydell, 2021/06/21
- [PULL 38/57] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/21
- [PULL 34/57] target/arm: Implement MVE VSUB, VMUL (scalar),
Peter Maydell <=
- [PULL 42/57] target/arm: Implement MVE VQADD, VQSUB (vector), Peter Maydell, 2021/06/21
- [PULL 24/57] target/arm: Implement MVE VMULH, Peter Maydell, 2021/06/21
- [PULL 14/57] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/21
- [PULL 13/57] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/21
- [PULL 18/57] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/21
- [PULL 22/57] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/21
- [PULL 27/57] target/arm: Implement MVE VABD, Peter Maydell, 2021/06/21
- [PULL 28/57] target/arm: Implement MVE VHADD, VHSUB, Peter Maydell, 2021/06/21
- [PULL 29/57] target/arm: Implement MVE VMULL, Peter Maydell, 2021/06/21
- [PULL 32/57] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/21