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Re: [PATCH v3 03/44] target/arm: Implement MVE VCLZ
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 03/44] target/arm: Implement MVE VCLZ |
Date: |
Mon, 21 Jun 2021 14:28:56 +0100 |
On Thu, 17 Jun 2021 at 13:16, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Implement the MVE VCLZ insn (and the necessary machinery
> for MVE 1-input vector ops).
>
> Note that for non-load instructions predication is always performed
> at a byte level granularity regardless of element size (R_ZLSJ),
> and so the masking logic here differs from that used in the VLDR
> and VSTR helpers.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> +#define DO_1OP(OP, ESIZE, TYPE, FN) \
> + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \
> + { \
> + TYPE *d = vd, *m = vm; \
> + uint16_t mask = mve_element_mask(env); \
> + unsigned e; \
> + unsigned const esize = sizeof(TYPE); \
> + for (e = 0; e < 16 / esize; e++, mask >>= esize) { \
> + mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \
> + } \
> + mve_advance_vpt(env); \
> + }
Just noticed I didn't quite get the refactoring from "use sizeof(TYPE)"
to "take ESIZE" right here, so we currently do both (correct behaviour,
but oddly written). I'm going to squash in this trivial fixup:
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -265,8 +265,7 @@ static inline void unknown_mergemask_type(void *d,
uint64_t r, uint16_t mask)
TYPE *d = vd, *m = vm; \
uint16_t mask = mve_element_mask(env); \
unsigned e; \
- unsigned const esize = sizeof(TYPE); \
- for (e = 0; e < 16 / esize; e++, mask >>= esize) { \
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \
} \
mve_advance_vpt(env); \
thanks
-- PMM
- [PATCH v3 00/44] target/arm: First slice of MVE implementation, Peter Maydell, 2021/06/17
- [PATCH v3 02/44] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/17
- [PATCH v3 01/44] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/17
- [PATCH v3 04/44] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/17
- [PATCH v3 03/44] target/arm: Implement MVE VCLZ, Peter Maydell, 2021/06/17
- [PATCH v3 07/44] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/17
- [PATCH v3 05/44] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/17
- [PATCH v3 06/44] target/arm: Implement MVE VMVN (register), Peter Maydell, 2021/06/17
- [PATCH v3 08/44] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/17
- [PATCH v3 11/44] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR, Peter Maydell, 2021/06/17
- [PATCH v3 09/44] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/17
- [PATCH v3 10/44] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/17
- [PATCH v3 14/44] target/arm: Implement MVE VRMULH, Peter Maydell, 2021/06/17
- [PATCH v3 12/44] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/17