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[PULL 13/37] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL
From: |
Cornelia Huck |
Subject: |
[PULL 13/37] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL |
Date: |
Mon, 21 Jun 2021 11:58:18 +0200 |
From: David Hildenbrand <david@redhat.com>
Fortunately, we only need the Doubleword implementation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-13-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/s390x/insn-data.def | 2 ++
target/s390x/translate_vx.c.inc | 50 +++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def
index 1634a6bc5aec..1a3ae7e7e77d 100644
--- a/target/s390x/insn-data.def
+++ b/target/s390x/insn-data.def
@@ -1151,6 +1151,8 @@
F(0xe7a7, VMO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
/* VECTOR MULTIPLY LOGICAL ODD */
F(0xe7a5, VMLO, VRR_c, V, 0, 0, 0, 0, vm, 0, IF_VEC)
+/* VECTOR MULTIPLY SUM LOGICAL */
+ F(0xe7b8, VMSL, VRR_d, VE, 0, 0, 0, 0, vmsl, 0, IF_VEC)
/* VECTOR NAND */
F(0xe76e, VNN, VRR_c, VE, 0, 0, 0, 0, vnn, 0, IF_VEC)
/* VECTOR NOR */
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index 96283d4ddb9a..6e75b40eb8ec 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -1779,6 +1779,56 @@ static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
return DISAS_NEXT;
}
+static DisasJumpType op_vmsl(DisasContext *s, DisasOps *o)
+{
+ TCGv_i64 l1, h1, l2, h2;
+
+ if (get_field(s, m4) != ES_64) {
+ gen_program_exception(s, PGM_SPECIFICATION);
+ return DISAS_NORETURN;
+ }
+
+ l1 = tcg_temp_new_i64();
+ h1 = tcg_temp_new_i64();
+ l2 = tcg_temp_new_i64();
+ h2 = tcg_temp_new_i64();
+
+ /* Multipy both even elements from v2 and v3 */
+ read_vec_element_i64(l1, get_field(s, v2), 0, ES_64);
+ read_vec_element_i64(h1, get_field(s, v3), 0, ES_64);
+ tcg_gen_mulu2_i64(l1, h1, l1, h1);
+ /* Shift result left by one (x2) if requested */
+ if (extract32(get_field(s, m6), 3, 1)) {
+ tcg_gen_add2_i64(l1, h1, l1, h1, l1, h1);
+ }
+
+ /* Multipy both odd elements from v2 and v3 */
+ read_vec_element_i64(l2, get_field(s, v2), 1, ES_64);
+ read_vec_element_i64(h2, get_field(s, v3), 1, ES_64);
+ tcg_gen_mulu2_i64(l2, h2, l2, h2);
+ /* Shift result left by one (x2) if requested */
+ if (extract32(get_field(s, m6), 2, 1)) {
+ tcg_gen_add2_i64(l2, h2, l2, h2, l2, h2);
+ }
+
+ /* Add both intermediate results */
+ tcg_gen_add2_i64(l1, h1, l1, h1, l2, h2);
+ /* Add whole v4 */
+ read_vec_element_i64(h2, get_field(s, v4), 0, ES_64);
+ read_vec_element_i64(l2, get_field(s, v4), 1, ES_64);
+ tcg_gen_add2_i64(l1, h1, l1, h1, l2, h2);
+
+ /* Store final result into v1. */
+ write_vec_element_i64(h1, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(l1, get_field(s, v1), 1, ES_64);
+
+ tcg_temp_free_i64(l1);
+ tcg_temp_free_i64(h1);
+ tcg_temp_free_i64(l2);
+ tcg_temp_free_i64(h2);
+ return DISAS_NEXT;
+}
+
static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
{
gen_gvec_fn_3(nand, ES_8, get_field(s, v1),
--
2.31.1
- [PULL 04/37] s390x/tcg: Simplify vop64_3() handling, (continued)
- [PULL 04/37] s390x/tcg: Simplify vop64_3() handling, Cornelia Huck, 2021/06/21
- [PULL 05/37] s390x/tcg: Simplify vop64_2() handling, Cornelia Huck, 2021/06/21
- [PULL 07/37] s390x/tcg: Simplify vftci64() handling, Cornelia Huck, 2021/06/21
- [PULL 06/37] s390x/tcg: Simplify vfc64() handling, Cornelia Huck, 2021/06/21
- [PULL 08/37] s390x/tcg: Simplify vfma64() handling, Cornelia Huck, 2021/06/21
- [PULL 10/37] s390x/tcg: Simplify vflr64() handling, Cornelia Huck, 2021/06/21
- [PULL 09/37] s390x/tcg: Simplify vfll32() handling, Cornelia Huck, 2021/06/21
- [PULL 11/37] s390x/tcg: Simplify wfc64() handling, Cornelia Huck, 2021/06/21
- [PULL 12/37] s390x/tcg: Implement VECTOR BIT PERMUTE, Cornelia Huck, 2021/06/21
- [PULL 14/37] s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 13/37] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL,
Cornelia Huck <=
- [PULL 15/37] s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT), Cornelia Huck, 2021/06/21
- [PULL 16/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *, Cornelia Huck, 2021/06/21
- [PULL 18/37] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED, Cornelia Huck, 2021/06/21
- [PULL 17/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, Cornelia Huck, 2021/06/21
- [PULL 19/37] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED, Cornelia Huck, 2021/06/21
- [PULL 21/37] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE, Cornelia Huck, 2021/06/21
- [PULL 20/37] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION, Cornelia Huck, 2021/06/21
- [PULL 23/37] s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 24/37] s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM), Cornelia Huck, 2021/06/21
- [PULL 22/37] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT), Cornelia Huck, 2021/06/21