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[PULL 18/33] tcg/tci: Implement andc, orc, eqv, nand, nor
From: |
Richard Henderson |
Subject: |
[PULL 18/33] tcg/tci: Implement andc, orc, eqv, nand, nor |
Date: |
Sat, 19 Jun 2021 11:14:37 -0700 |
These were already present in tcg-target.c.inc,
but not in the interpreter.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 20 ++++++++++----------
tcg/tci.c | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index 5c79bfcf49..ac8c2d85bd 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -68,20 +68,20 @@
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
+#define TCG_TARGET_HAS_andc_i32 1
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_extract_i32 0
#define TCG_TARGET_HAS_sextract_i32 0
#define TCG_TARGET_HAS_extract2_i32 0
-#define TCG_TARGET_HAS_eqv_i32 0
-#define TCG_TARGET_HAS_nand_i32 0
-#define TCG_TARGET_HAS_nor_i32 0
+#define TCG_TARGET_HAS_eqv_i32 1
+#define TCG_TARGET_HAS_nand_i32 1
+#define TCG_TARGET_HAS_nor_i32 1
#define TCG_TARGET_HAS_clz_i32 0
#define TCG_TARGET_HAS_ctz_i32 0
#define TCG_TARGET_HAS_ctpop_i32 0
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_not_i32 1
-#define TCG_TARGET_HAS_orc_i32 0
+#define TCG_TARGET_HAS_orc_i32 1
#define TCG_TARGET_HAS_rot_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_muls2_i32 0
@@ -109,16 +109,16 @@
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
-#define TCG_TARGET_HAS_nand_i64 0
-#define TCG_TARGET_HAS_nor_i64 0
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_HAS_eqv_i64 1
+#define TCG_TARGET_HAS_nand_i64 1
+#define TCG_TARGET_HAS_nor_i64 1
#define TCG_TARGET_HAS_clz_i64 0
#define TCG_TARGET_HAS_ctz_i64 0
#define TCG_TARGET_HAS_ctpop_i64 0
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_not_i64 1
-#define TCG_TARGET_HAS_orc_i64 0
+#define TCG_TARGET_HAS_orc_i64 1
#define TCG_TARGET_HAS_rot_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_muls2_i64 0
diff --git a/tcg/tci.c b/tcg/tci.c
index 2374c04d6b..8af82c7da7 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -531,6 +531,36 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = regs[r1] ^ regs[r2];
break;
+#if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64
+ CASE_32_64(andc)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] & ~regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64
+ CASE_32_64(orc)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = regs[r1] | ~regs[r2];
+ break;
+#endif
+#if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64
+ CASE_32_64(eqv)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] ^ regs[r2]);
+ break;
+#endif
+#if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64
+ CASE_32_64(nand)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] & regs[r2]);
+ break;
+#endif
+#if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64
+ CASE_32_64(nor)
+ tci_args_rrr(insn, &r0, &r1, &r2);
+ regs[r0] = ~(regs[r1] | regs[r2]);
+ break;
+#endif
/* Arithmetic operations (32 bit). */
@@ -1121,6 +1151,16 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_nand_i32:
+ case INDEX_op_nand_i64:
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
case INDEX_op_div_i32:
case INDEX_op_div_i64:
case INDEX_op_rem_i32:
--
2.25.1
- [PULL 03/33] accel/tcg/plugin-gen: Drop inline markers, (continued)
- [PULL 03/33] accel/tcg/plugin-gen: Drop inline markers, Richard Henderson, 2021/06/19
- [PULL 04/33] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb, Richard Henderson, 2021/06/19
- [PULL 06/33] tcg: Store the TCGHelperInfo in the TCGOp for call, Richard Henderson, 2021/06/19
- [PULL 05/33] accel/tcg: Add tcg call flags to plugins helpers, Richard Henderson, 2021/06/19
- [PULL 07/33] tcg: Add tcg_call_func, Richard Henderson, 2021/06/19
- [PULL 08/33] tcg: Build ffi data structures for helpers, Richard Henderson, 2021/06/19
- [PULL 09/33] tcg/tci: Improve tcg_target_call_clobber_regs, Richard Henderson, 2021/06/19
- [PULL 02/33] tcg: Add tcg_call_flags, Richard Henderson, 2021/06/19
- [PULL 10/33] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order, Richard Henderson, 2021/06/19
- [PULL 11/33] tcg/tci: Use ffi for calls, Richard Henderson, 2021/06/19
- [PULL 18/33] tcg/tci: Implement andc, orc, eqv, nand, nor,
Richard Henderson <=
- [PULL 12/33] tcg/tci: Reserve r13 for a temporary, Richard Henderson, 2021/06/19
- [PULL 30/33] tcg: Allocate sufficient storage in temp_allocate_frame, Richard Henderson, 2021/06/19
- [PULL 26/33] tcg/tci: Use {set,clear}_helper_retaddr, Richard Henderson, 2021/06/19
- [PULL 25/33] tcg/tci: Remove the qemu_ld/st_type macros, Richard Henderson, 2021/06/19
- [PULL 31/33] tcg: Restart when exhausting the stack frame, Richard Henderson, 2021/06/19
- [PULL 14/33] tcg/tci: Remove tci_write_reg, Richard Henderson, 2021/06/19
- [PULL 17/33] tcg/tci: Implement movcond, Richard Henderson, 2021/06/19
- [PULL 19/33] tcg/tci: Implement extract, sextract, Richard Henderson, 2021/06/19
- [PULL 22/33] tcg/tci: Implement add2, sub2, Richard Henderson, 2021/06/19
- [PULL 13/33] tcg/tci: Emit setcond before brcond, Richard Henderson, 2021/06/19