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From: | Richard Henderson |
Subject: | Re: [PATCH 1/9] target/mips: Do not abort on invalid instruction |
Date: | Fri, 18 Jun 2021 15:30:34 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 |
On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote:
On real hardware an invalid instruction doesn't halt the world, but usually triggers a RESERVED INSTRUCTION exception. TCG guest code shouldn't abort QEMU anyway. Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org> --- target/mips/tcg/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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