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[PATCH v3 31/44] target/arm: Implement MVE VQADD, VQSUB (vector)
From: |
Peter Maydell |
Subject: |
[PATCH v3 31/44] target/arm: Implement MVE VQADD, VQSUB (vector) |
Date: |
Thu, 17 Jun 2021 13:16:15 +0100 |
Implement the vector forms of the MVE VQADD and VQSUB insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-mve.h | 16 ++++++++++++++++
target/arm/mve.decode | 5 +++++
target/arm/mve_helper.c | 14 ++++++++++++++
target/arm/translate-mve.c | 4 ++++
4 files changed, 39 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index c4e766c6511..93847fc04ad 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -153,6 +153,22 @@ DEF_HELPER_FLAGS_4(mve_vqrdmulhb, TCG_CALL_NO_WG, void,
env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqrdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqrdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqsubsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqsubsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 9860d43f73c..80fa647c08f 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -116,6 +116,11 @@ VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 .
0 ... 0 @2op
VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op
VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op
+VQADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op
+VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op
+VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
+VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
+
# Vector miscellaneous
VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index d17c5e4588b..bba3c1c1ee3 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -578,6 +578,20 @@ DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B)
DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H)
DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W)
+DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B)
+DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H)
+DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W)
+DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B)
+DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H)
+DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W)
+
+DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B)
+DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H)
+DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W)
+DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B)
+DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H)
+DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W)
+
#define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \
void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \
uint32_t rm) \
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index ec9a9852868..9f59ed591bc 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -398,6 +398,10 @@ DO_2OP(VMULL_TS, vmullts)
DO_2OP(VMULL_TU, vmulltu)
DO_2OP(VQDMULH, vqdmulh)
DO_2OP(VQRDMULH, vqrdmulh)
+DO_2OP(VQADD_S, vqadds)
+DO_2OP(VQADD_U, vqaddu)
+DO_2OP(VQSUB_S, vqsubs)
+DO_2OP(VQSUB_U, vqsubu)
static bool do_2op_scalar(DisasContext *s, arg_2scalar *a,
MVEGenTwoOpScalarFn fn)
--
2.20.1
- [PATCH v3 22/44] target/arm: Implement MVE VADD (scalar), (continued)
- [PATCH v3 22/44] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 25/44] target/arm: Implement MVE VBRSR, Peter Maydell, 2021/06/17
- [PATCH v3 26/44] target/arm: Implement MVE VPST, Peter Maydell, 2021/06/17
- [PATCH v3 20/44] target/arm: Implement MVE VMLSLDAV, Peter Maydell, 2021/06/17
- [PATCH v3 21/44] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/17
- [PATCH v3 24/44] target/arm: Implement MVE VHADD, VHSUB (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 27/44] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/17
- [PATCH v3 23/44] target/arm: Implement MVE VSUB, VMUL (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 28/44] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar), Peter Maydell, 2021/06/17
- [PATCH v3 29/44] target/arm: Implement MVE VQDMULL scalar, Peter Maydell, 2021/06/17
- [PATCH v3 31/44] target/arm: Implement MVE VQADD, VQSUB (vector),
Peter Maydell <=
- [PATCH v3 30/44] target/arm: Implement MVE VQDMULH, VQRDMULH (vector), Peter Maydell, 2021/06/17
- [PATCH v3 32/44] target/arm: Implement MVE VQSHL (vector), Peter Maydell, 2021/06/17
- [PATCH v3 33/44] target/arm: Implement MVE VQRSHL, Peter Maydell, 2021/06/17
- [PATCH v3 35/44] target/arm: Implmement MVE VRSHL, Peter Maydell, 2021/06/17
- [PATCH v3 37/44] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH, Peter Maydell, 2021/06/17
- [PATCH v3 36/44] target/arm: Implement MVE VQDMLADH and VQRDMLADH, Peter Maydell, 2021/06/17
- [PATCH v3 39/44] target/arm: Implement MVE VRHADD, Peter Maydell, 2021/06/17
- [PATCH v3 40/44] target/arm: Implement MVE VADC, VSBC, Peter Maydell, 2021/06/17