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[PULL 21/28] target/arm: Implement MVE LCTP
From: |
Peter Maydell |
Subject: |
[PULL 21/28] target/arm: Implement MVE LCTP |
Date: |
Tue, 15 Jun 2021 16:43:58 +0100 |
Implement the MVE LCTP instruction.
We put its decode and implementation with the other
low-overhead-branch insns because although it is only present if MVE
is implemented it is logically in the same group as the other LOB
insns.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210614151007.4545-7-peter.maydell@linaro.org
---
target/arm/t32.decode | 2 ++
target/arm/translate.c | 24 ++++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 8b2c487fa7a..087e514e0ac 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -674,5 +674,7 @@ BL 1111 0. .......... 11.1 ............
@branch24
DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001
WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=%lob_imm
LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=%lob_imm
+
+ LCTP 1111 0 0000 000 1111 1110 0000 0000 0001
]
}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f1c2074fa4a..c49561590c9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8191,6 +8191,30 @@ static bool trans_LE(DisasContext *s, arg_LE *a)
return true;
}
+static bool trans_LCTP(DisasContext *s, arg_LCTP *a)
+{
+ /*
+ * M-profile Loop Clear with Tail Predication. Since our implementation
+ * doesn't cache branch information, all we need to do is reset
+ * FPSCR.LTPSIZE to 4.
+ */
+ TCGv_i32 ltpsize;
+
+ if (!dc_isar_feature(aa32_lob, s) ||
+ !dc_isar_feature(aa32_mve, s)) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ ltpsize = tcg_const_i32(4);
+ store_cpu_field(ltpsize, v7m.ltpsize);
+ return true;
+}
+
+
static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
{
TCGv_i32 addr, tmp;
--
2.20.1
- [PULL 08/28] hw/intc/armv7m_nvic: Remove stale comment, (continued)
- [PULL 08/28] hw/intc/armv7m_nvic: Remove stale comment, Peter Maydell, 2021/06/15
- [PULL 12/28] target/arm: Fix mte page crossing test, Peter Maydell, 2021/06/15
- [PULL 11/28] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors, Peter Maydell, 2021/06/15
- [PULL 13/28] hw/arm: gsj add i2c comments, Peter Maydell, 2021/06/15
- [PULL 09/28] hw/acpi: Provide stub version of acpi_ghes_record_errors(), Peter Maydell, 2021/06/15
- [PULL 14/28] hw/arm: gsj add pca9548, Peter Maydell, 2021/06/15
- [PULL 15/28] hw/arm: quanta-q71l add pca954x muxes, Peter Maydell, 2021/06/15
- [PULL 10/28] hw/acpi: Provide function acpi_ghes_present(), Peter Maydell, 2021/06/15
- [PULL 19/28] target/arm: Add handling for PSR.ECI/ICI, Peter Maydell, 2021/06/15
- [PULL 20/28] target/arm: Let vfp_access_check() handle late NOCP checks, Peter Maydell, 2021/06/15
- [PULL 21/28] target/arm: Implement MVE LCTP,
Peter Maydell <=
- [PULL 22/28] target/arm: Implement MVE WLSTP insn, Peter Maydell, 2021/06/15
- [PULL 24/28] target/arm: Implement MVE LETP insn, Peter Maydell, 2021/06/15
- [PULL 28/28] include/qemu/int128.h: Add function to create Int128 from int64_t, Peter Maydell, 2021/06/15
- [PULL 17/28] target/arm: Enable FPSCR.QC bit for MVE, Peter Maydell, 2021/06/15
- [PULL 18/28] target/arm: Handle VPR semantics in existing code, Peter Maydell, 2021/06/15
- [PULL 23/28] target/arm: Implement MVE DLSTP, Peter Maydell, 2021/06/15
- [PULL 16/28] target/arm: Provide and use H8 and H1_8 macros, Peter Maydell, 2021/06/15
- [PULL 26/28] target/arm: Move expand_pred_b() data to vec_helper.c, Peter Maydell, 2021/06/15
- [PULL 27/28] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations, Peter Maydell, 2021/06/15
- [PULL 25/28] target/arm: Add framework for MVE decode, Peter Maydell, 2021/06/15