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[PATCH v2 55/57] target/arm: Implement MVE VHCADD
From: |
Peter Maydell |
Subject: |
[PATCH v2 55/57] target/arm: Implement MVE VHCADD |
Date: |
Mon, 14 Jun 2021 16:10:05 +0100 |
Implement the MVE VHCADD insn, which is similar to VCADD
but performs a halving step. This one overlaps with VADC.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 8 ++++++--
target/arm/mve_helper.c | 2 ++
target/arm/translate-mve.c | 4 +++-
4 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index b8ad3df9cc8..161308b67e6 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -259,6 +259,14 @@ DEF_HELPER_FLAGS_4(mve_vcadd270b, TCG_CALL_NO_WG, void,
env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhcadd90b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhcadd90w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vhcadd270b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vhcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index afe60078649..695097dcca4 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -160,8 +160,12 @@ VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 .
0 ... 1 @2op_sz28
VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op
VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op
-VADC 1110 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz
-VADCI 1110 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz
+{
+ VADC 1110 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz
+ VADCI 1110 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz
+ VHCADD90 1110 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op
+ VHCADD270 1110 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op
+}
{
VSBC 1111 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index e2daf34f38e..e5b8016e377 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -632,6 +632,8 @@ void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void
*vn, void *vm)
DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD)
DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB)
+DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s)
+DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s)
static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool
*s)
{
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index c9f5ef73955..ca619dad14a 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -423,10 +423,12 @@ DO_2OP(VRHADD_U, vrhaddu)
/*
* VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose
* so we can reuse the DO_2OP macro. (Our implementation calculates the
- * "expected" results in this case.)
+ * "expected" results in this case.) Similarly for VHCADD.
*/
DO_2OP(VCADD90, vcadd90)
DO_2OP(VCADD270, vcadd270)
+DO_2OP(VHCADD90, vhcadd90)
+DO_2OP(VHCADD270, vhcadd270)
static bool trans_VQDMULLB(DisasContext *s, arg_2op *a)
{
--
2.20.1
- [PATCH v2 45/57] target/arm: Implement MVE VQSHL (vector), (continued)
- [PATCH v2 45/57] target/arm: Implement MVE VQSHL (vector), Peter Maydell, 2021/06/14
- [PATCH v2 40/57] target/arm: Implement MVE VQADD and VQSUB, Peter Maydell, 2021/06/14
- [PATCH v2 46/57] target/arm: Implement MVE VQRSHL, Peter Maydell, 2021/06/14
- [PATCH v2 49/57] target/arm: Implement MVE VQDMLADH and VQRDMLADH, Peter Maydell, 2021/06/14
- [PATCH v2 51/57] target/arm: Implement MVE VQDMULL (vector), Peter Maydell, 2021/06/14
- [PATCH v2 50/57] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH, Peter Maydell, 2021/06/14
- [PATCH v2 48/57] target/arm: Implmement MVE VRSHL, Peter Maydell, 2021/06/14
- [PATCH v2 44/57] target/arm: Implement MVE VQADD, VQSUB (vector), Peter Maydell, 2021/06/14
- [PATCH v2 47/57] target/arm: Implement MVE VSHL insn, Peter Maydell, 2021/06/14
- [PATCH v2 55/57] target/arm: Implement MVE VHCADD,
Peter Maydell <=
- [PATCH v2 52/57] target/arm: Implement MVE VRHADD, Peter Maydell, 2021/06/14
- [PATCH v2 57/57] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE, Peter Maydell, 2021/06/14
- [PATCH v2 54/57] target/arm: Implement MVE VCADD, Peter Maydell, 2021/06/14
- [PATCH v2 53/57] target/arm: Implement MVE VADC, VSBC, Peter Maydell, 2021/06/14
- [PATCH v2 56/57] target/arm: Implement MVE VADDV, Peter Maydell, 2021/06/14
- Re: [PATCH v2 00/57] target/arm: First slice of MVE implementation, no-reply, 2021/06/14
- Re: [PATCH v2 00/57] target/arm: First slice of MVE implementation, Richard Henderson, 2021/06/14