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[PATCH v1 0/3] RISC-V ACLINT Support
From: |
Anup Patel |
Subject: |
[PATCH v1 0/3] RISC-V ACLINT Support |
Date: |
Sat, 12 Jun 2021 21:36:12 +0530 |
The RISC-V Advanced Core Local Interruptor (ACLINT) is an improvement
over the SiFive CLINT but also maintains backward compatibility with
the SiFive CLINT.
Latest RISC-V ACLINT specification (will be frozen in a month) can be
found at:
https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
This series:
1) Replaces SiFive CLINT implementation with RISC-V ACLINT
2) Refactors RISC-V virt machine FDT generation
3) Adds optional full ACLINT support in QEMU RISC-V virt machine
This series can be found in the riscv_aclint_v1 branch at:
https://github.com/avpatel/qemu.git
To test series, we require OpenSBI and Linux with ACLINT support which
can be found in riscv_aclint_v1 branch at:
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git
Anup Patel (3):
hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT
hw/riscv: virt: Re-factor FDT generation
hw/riscv: virt: Add optional ACLINT support to virt machine
hw/intc/Kconfig | 2 +-
hw/intc/meson.build | 2 +-
hw/intc/riscv_aclint.c | 374 +++++++++++++++++++
hw/intc/sifive_clint.c | 266 --------------
hw/riscv/Kconfig | 10 +-
hw/riscv/microchip_pfsoc.c | 12 +-
hw/riscv/sifive_e.c | 12 +-
hw/riscv/sifive_u.c | 14 +-
hw/riscv/spike.c | 15 +-
hw/riscv/virt.c | 635 ++++++++++++++++++++++-----------
include/hw/intc/riscv_aclint.h | 73 ++++
include/hw/intc/sifive_clint.h | 60 ----
include/hw/riscv/virt.h | 2 +
13 files changed, 923 insertions(+), 554 deletions(-)
create mode 100644 hw/intc/riscv_aclint.c
delete mode 100644 hw/intc/sifive_clint.c
create mode 100644 include/hw/intc/riscv_aclint.h
delete mode 100644 include/hw/intc/sifive_clint.h
--
2.25.1
- [PATCH v1 0/3] RISC-V ACLINT Support,
Anup Patel <=