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[PULL 07/32] hw/riscv: Use macros for BIOS image names
From: |
Alistair Francis |
Subject: |
[PULL 07/32] hw/riscv: Use macros for BIOS image names |
Date: |
Tue, 8 Jun 2021 10:29:22 +1000 |
From: Bin Meng <bin.meng@windriver.com>
The OpenSBI BIOS image names are used by many RISC-V machines.
Let's define macros for them.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210430071302.1489082-7-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/boot.h | 5 +++++
hw/riscv/sifive_u.c | 6 ++----
hw/riscv/spike.c | 6 ++----
hw/riscv/virt.c | 6 ++----
4 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 11a21dd584..0e89400b09 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -24,6 +24,11 @@
#include "hw/loader.h"
#include "hw/riscv/riscv_hart.h"
+#define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin"
+#define RISCV32_BIOS_ELF "opensbi-riscv32-generic-fw_dynamic.elf"
+#define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin"
+#define RISCV64_BIOS_ELF "opensbi-riscv64-generic-fw_dynamic.elf"
+
bool riscv_is_32bit(RISCVHartArrayState *harts);
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index a32a95d58f..273c86418c 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -560,12 +560,10 @@ static void sifive_u_machine_init(MachineState *machine)
if (riscv_is_32bit(&s->soc.u_cpus)) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv32-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv64-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV64_BIOS_BIN, start_addr, NULL);
}
if (machine->kernel_filename) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 4b08816dfa..fead77f0c4 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -258,13 +258,11 @@ static void spike_board_init(MachineState *machine)
*/
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv32-generic-fw_dynamic.elf",
- memmap[SPIKE_DRAM].base,
+ RISCV32_BIOS_ELF, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv64-generic-fw_dynamic.elf",
- memmap[SPIKE_DRAM].base,
+ RISCV64_BIOS_ELF, memmap[SPIKE_DRAM].base,
htif_symbol_callback);
}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 560216d217..4a3cd2599a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -681,12 +681,10 @@ static void virt_machine_init(MachineState *machine)
if (riscv_is_32bit(&s->soc[0])) {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv32-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV32_BIOS_BIN, start_addr, NULL);
} else {
firmware_end_addr = riscv_find_and_load_firmware(machine,
- "opensbi-riscv64-generic-fw_dynamic.bin",
- start_addr, NULL);
+ RISCV64_BIOS_BIN, start_addr, NULL);
}
if (machine->kernel_filename) {
--
2.31.1
- [PULL 00/32] riscv-to-apply queue, Alistair Francis, 2021/06/07
- [PULL 01/32] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper, Alistair Francis, 2021/06/07
- [PULL 02/32] hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper, Alistair Francis, 2021/06/07
- [PULL 03/32] hw/riscv: Support the official CLINT DT bindings, Alistair Francis, 2021/06/07
- [PULL 04/32] hw/riscv: Support the official PLIC DT bindings, Alistair Francis, 2021/06/07
- [PULL 05/32] docs/system/riscv: Correct the indentation level of supported devices, Alistair Francis, 2021/06/07
- [PULL 06/32] docs/system/riscv: sifive_u: Document '-dtb' usage, Alistair Francis, 2021/06/07
- [PULL 07/32] hw/riscv: Use macros for BIOS image names,
Alistair Francis <=
- [PULL 08/32] hw/riscv: microchip_pfsoc: Support direct kernel boot, Alistair Francis, 2021/06/07
- [PULL 09/32] target/riscv: fix wfi exception behavior, Alistair Francis, 2021/06/07
- [PULL 10/32] docs/system: Move the RISC-V -bios information to removed, Alistair Francis, 2021/06/07
- [PULL 11/32] target/riscv: Do not include 'pmp.h' in user emulation, Alistair Francis, 2021/06/07
- [PULL 12/32] target/riscv: Remove unnecessary riscv_*_names[] declaration, Alistair Francis, 2021/06/07
- [PULL 13/32] target/riscv: Dump CSR mscratch/sscratch/satp, Alistair Francis, 2021/06/07
- [PULL 14/32] target/riscv/pmp: Add assert for ePMP operations, Alistair Francis, 2021/06/07
- [PULL 15/32] target/riscv: Pass the same value to oprsz and maxsz., Alistair Francis, 2021/06/07
- [PULL 16/32] target/riscv: reformat @sh format encoding for B-extension, Alistair Francis, 2021/06/07
- [PULL 17/32] target/riscv: rvb: count leading/trailing zeros, Alistair Francis, 2021/06/07