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[PATCH v16 81/99] target/arm: tcg-sve: rename the narrow_vq and change_e
From: |
Alex Bennée |
Subject: |
[PATCH v16 81/99] target/arm: tcg-sve: rename the narrow_vq and change_el functions |
Date: |
Fri, 4 Jun 2021 16:52:54 +0100 |
From: Claudio Fontana <cfontana@suse.de>
make them canonical for the module name.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/tcg/tcg-sve.h | 6 +++---
linux-user/syscall.c | 2 +-
target/arm/cpu-exceptions-aa64.c | 2 +-
target/arm/tcg/cpregs.c | 2 +-
target/arm/tcg/helper-a64.c | 2 +-
target/arm/tcg/tcg-sve.c | 6 +++---
6 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h
index 5855bb4289..46e42d1139 100644
--- a/target/arm/tcg/tcg-sve.h
+++ b/target/arm/tcg/tcg-sve.h
@@ -21,9 +21,9 @@ uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map,
bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq,
Error **errp);
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
+void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq);
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
- int new_el, bool el0_a64);
+void tcg_sve_change_el(CPUARMState *env, int old_el,
+ int new_el, bool el0_a64);
#endif /* TCG_SVE_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index db4b7b1e46..4cfbe72b21 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -10877,7 +10877,7 @@ static abi_long do_syscall1(void *cpu_env, int num,
abi_long arg1,
vq = MIN(vq, cpu->sve_max_vq);
if (vq < old_vq) {
- aarch64_sve_narrow_vq(env, vq);
+ tcg_sve_narrow_vq(env, vq);
}
env->vfp.zcr_el[1] = vq - 1;
arm_rebuild_hflags(env);
diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-aa64.c
index adaf3bab17..1a3e1d6458 100644
--- a/target/arm/cpu-exceptions-aa64.c
+++ b/target/arm/cpu-exceptions-aa64.c
@@ -119,7 +119,7 @@ void arm_cpu_do_interrupt_aarch64(CPUState *cs)
* Note that new_el can never be 0. If cur_el is 0, then
* el0_a64 is is_a64(), else el0_a64 is ignored.
*/
- aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
+ tcg_sve_change_el(env, cur_el, new_el, is_a64(env));
}
if (cur_el < new_el) {
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index 9d3c9ae841..9d4ac66281 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -5814,7 +5814,7 @@ static void zcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
*/
new_len = sve_zcr_len_for_el(env, cur_el);
if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
+ tcg_sve_narrow_vq(env, new_len + 1);
}
}
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index f261f13b2c..e169c03c63 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -1042,7 +1042,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t
new_pc)
* Note that cur_el can never be 0. If new_el is 0, then
* el0_a64 is return_to_aa64, else el0_a64 is ignored.
*/
- aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
+ tcg_sve_change_el(env, cur_el, new_el, return_to_aa64);
qemu_mutex_lock_iothread();
arm_call_el_change_hook(env_archcpu(env));
diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c
index 908d2c2f2c..25d5a5867c 100644
--- a/target/arm/tcg/tcg-sve.c
+++ b/target/arm/tcg/tcg-sve.c
@@ -95,7 +95,7 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map,
uint32_t max_vq,
* may well be cheaper than conditionals to restrict the operation
* to the relevant portion of a uint16_t[16].
*/
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
+void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq)
{
int i, j;
uint64_t pmask;
@@ -124,7 +124,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
/*
* Notice a change in SVE vector size when changing EL.
*/
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
+void tcg_sve_change_el(CPUARMState *env, int old_el,
int new_el, bool el0_a64)
{
ARMCPU *cpu = env_archcpu(env);
@@ -162,6 +162,6 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el,
/* When changing vector length, clear inaccessible state. */
if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
+ tcg_sve_narrow_vq(env, new_len + 1);
}
}
--
2.20.1
- [PATCH v16 48/99] target/arm: remove now useless ifndef from fp_exception_el, (continued)
- [PATCH v16 48/99] target/arm: remove now useless ifndef from fp_exception_el, Alex Bennée, 2021/06/04
- [PATCH v16 90/99] XXX target/arm: experiment refactoring cpu "max", Alex Bennée, 2021/06/04
- [PATCH v16 49/99] target/arm: make further preparation for the exception code to move, Alex Bennée, 2021/06/04
- [PATCH v16 98/99] configure: allow the overriding of default-config in the build, Alex Bennée, 2021/06/04
- [PATCH v16 91/99] target/arm: tcg: remove superfluous CONFIG_TCG check, Alex Bennée, 2021/06/04
- [PATCH v16 22/99] target/arm: tcg: split m_helper user-only and sysemu-only parts, Alex Bennée, 2021/06/04
- [PATCH v16 81/99] target/arm: tcg-sve: rename the narrow_vq and change_el functions,
Alex Bennée <=
- [PATCH v16 66/99] tests: do not run qom-test on all machines for ARM KVM-only, Alex Bennée, 2021/06/04
- [PATCH v16 65/99] tests: device-introspect-test: cope with ARM TCG-only devices, Alex Bennée, 2021/06/04
- [PATCH v16 14/99] accel: add cpu_reset, Alex Bennée, 2021/06/04
- [PATCH v16 74/99] target/arm: cpu-sve: make cpu_sve_finalize_features return bool, Alex Bennée, 2021/06/04
- [PATCH v16 15/99] target/arm: move translate modules to tcg/, Alex Bennée, 2021/06/04
- [PATCH v16 50/99] target/arm: fix style of arm_cpu_do_interrupt functions before move, Alex Bennée, 2021/06/04