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[PATCH v16 53/99] target/arm: replace CONFIG_TCG with tcg_enabled
From: |
Alex Bennée |
Subject: |
[PATCH v16 53/99] target/arm: replace CONFIG_TCG with tcg_enabled |
Date: |
Fri, 4 Jun 2021 16:52:26 +0100 |
From: Claudio Fontana <cfontana@suse.de>
for "all" builds (tcg + kvm), we want to avoid doing
the psci and semihosting checks if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/cpu-sysemu.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 7569241339..e83d55b9f7 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -1141,22 +1141,22 @@ void arm_cpu_do_interrupt(CPUState *cs)
env->exception.syndrome);
}
-#ifdef CONFIG_TCG
- if (arm_is_psci_call(cpu, cs->exception_index)) {
- arm_handle_psci_call(cpu);
- qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
- return;
- }
- /*
- * Semihosting semantics depend on the register width of the code
- * that caused the exception, not the target exception level, so
- * must be handled here.
- */
- if (cs->exception_index == EXCP_SEMIHOST) {
- tcg_handle_semihosting(cs);
- return;
+ if (tcg_enabled()) {
+ if (arm_is_psci_call(cpu, cs->exception_index)) {
+ arm_handle_psci_call(cpu);
+ qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
+ return;
+ }
+ /*
+ * Semihosting semantics depend on the register width of the code
+ * that caused the exception, not the target exception level, so
+ * must be handled here.
+ */
+ if (cs->exception_index == EXCP_SEMIHOST) {
+ tcg_handle_semihosting(cs);
+ return;
+ }
}
-#endif /* CONFIG_TCG */
/*
* Hooks may change global state so BQL should be held, also the
* BQL needs to be held for any modification of
--
2.20.1
- Re: [PATCH v16 41/99] target/arm: new cpu32 ARM 32 bit CPU Class, (continued)
- [PATCH v16 33/99] target/arm: add temporary stub for arm_rebuild_hflags, Alex Bennée, 2021/06/04
- [PATCH v16 82/99] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve, Alex Bennée, 2021/06/04
- [PATCH v16 51/99] target/arm: move exception code out of tcg/helper.c, Alex Bennée, 2021/06/04
- [PATCH v16 99/99] gitlab: defend the new stripped down arm64 configs, Alex Bennée, 2021/06/04
- [PATCH v16 31/99] target/arm: tcg: add stubs for some helpers for non-tcg builds, Alex Bennée, 2021/06/04
- [PATCH v16 53/99] target/arm: replace CONFIG_TCG with tcg_enabled,
Alex Bennée <=
- [PATCH v16 68/99] target/arm: move kvm post init initialization to kvm cpu accel, Alex Bennée, 2021/06/04
- [PATCH v16 23/99] target/arm: only build psci for TCG, Alex Bennée, 2021/06/04
- [PATCH v16 67/99] target/arm: create kvm cpu accel class, Alex Bennée, 2021/06/04
- [PATCH v16 40/99] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code, Alex Bennée, 2021/06/04
- [PATCH v16 30/99] target/arm: only perform TCG cpu and machine inits if TCG enabled, Alex Bennée, 2021/06/04
- [PATCH v16 56/99] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Alex Bennée, 2021/06/04
- [PATCH v16 47/99] target/arm: move fp_exception_el out of TCG helpers, Alex Bennée, 2021/06/04
- [PATCH v16 89/99] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features, Alex Bennée, 2021/06/04