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[PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st
From: |
Richard Henderson |
Subject: |
[PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st |
Date: |
Tue, 1 Jun 2021 08:01:02 -0700 |
We can share this code between 32-bit and 64-bit loads and stores.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci.c | 183 +++++++++++++++++++++---------------------------------
1 file changed, 71 insertions(+), 112 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index eb9b1ab463..36558210a1 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -315,6 +315,73 @@ static bool tci_compare64(uint64_t u0, uint64_t u1,
TCGCond condition)
#define qemu_st_beq(X) \
cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr)
+static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+
+ switch (mop) {
+ case MO_UB:
+ return qemu_ld_ub;
+ case MO_SB:
+ return (int8_t)qemu_ld_ub;
+ case MO_LEUW:
+ return qemu_ld_leuw;
+ case MO_LESW:
+ return (int16_t)qemu_ld_leuw;
+ case MO_LEUL:
+ return qemu_ld_leul;
+ case MO_LESL:
+ return (int32_t)qemu_ld_leul;
+ case MO_LEQ:
+ return qemu_ld_leq;
+ case MO_BEUW:
+ return qemu_ld_beuw;
+ case MO_BESW:
+ return (int16_t)qemu_ld_beuw;
+ case MO_BEUL:
+ return qemu_ld_beul;
+ case MO_BESL:
+ return (int32_t)qemu_ld_beul;
+ case MO_BEQ:
+ return qemu_ld_beq;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val,
+ TCGMemOpIdx oi, const void *tb_ptr)
+{
+ MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE);
+
+ switch (mop) {
+ case MO_UB:
+ qemu_st_b(val);
+ break;
+ case MO_LEUW:
+ qemu_st_lew(val);
+ break;
+ case MO_LEUL:
+ qemu_st_lel(val);
+ break;
+ case MO_LEQ:
+ qemu_st_leq(val);
+ break;
+ case MO_BEUW:
+ qemu_st_bew(val);
+ break;
+ case MO_BEUL:
+ qemu_st_bel(val);
+ break;
+ case MO_BEQ:
+ qemu_st_beq(val);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
#if TCG_TARGET_REG_BITS == 64
# define CASE_32_64(x) \
case glue(glue(INDEX_op_, x), _i64): \
@@ -907,34 +974,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
tci_args_rrrm(insn, &r0, &r1, &r2, &oi);
taddr = tci_uint64(regs[r2], regs[r1]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp32 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp32 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp32 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp32 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp32 = qemu_ld_leul;
- break;
- case MO_BEUW:
- tmp32 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp32 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp32 = qemu_ld_beul;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr);
regs[r0] = tmp32;
break;
@@ -950,46 +990,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
taddr = tci_uint64(regs[r3], regs[r2]);
oi = regs[r4];
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) {
- case MO_UB:
- tmp64 = qemu_ld_ub;
- break;
- case MO_SB:
- tmp64 = (int8_t)qemu_ld_ub;
- break;
- case MO_LEUW:
- tmp64 = qemu_ld_leuw;
- break;
- case MO_LESW:
- tmp64 = (int16_t)qemu_ld_leuw;
- break;
- case MO_LEUL:
- tmp64 = qemu_ld_leul;
- break;
- case MO_LESL:
- tmp64 = (int32_t)qemu_ld_leul;
- break;
- case MO_LEQ:
- tmp64 = qemu_ld_leq;
- break;
- case MO_BEUW:
- tmp64 = qemu_ld_beuw;
- break;
- case MO_BESW:
- tmp64 = (int16_t)qemu_ld_beuw;
- break;
- case MO_BEUL:
- tmp64 = qemu_ld_beul;
- break;
- case MO_BESL:
- tmp64 = (int32_t)qemu_ld_beul;
- break;
- case MO_BEQ:
- tmp64 = qemu_ld_beq;
- break;
- default:
- g_assert_not_reached();
- }
+ tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr);
if (TCG_TARGET_REG_BITS == 32) {
tci_write_reg64(regs, r1, r0, tmp64);
} else {
@@ -1006,25 +1007,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
taddr = tci_uint64(regs[r2], regs[r1]);
}
tmp32 = regs[r0];
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp32);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp32);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp32);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp32);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp32);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp32, oi, tb_ptr);
break;
case INDEX_op_qemu_st_i64:
@@ -1043,31 +1026,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
}
tmp64 = tci_uint64(regs[r1], regs[r0]);
}
- switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {
- case MO_UB:
- qemu_st_b(tmp64);
- break;
- case MO_LEUW:
- qemu_st_lew(tmp64);
- break;
- case MO_LEUL:
- qemu_st_lel(tmp64);
- break;
- case MO_LEQ:
- qemu_st_leq(tmp64);
- break;
- case MO_BEUW:
- qemu_st_bew(tmp64);
- break;
- case MO_BEUL:
- qemu_st_bel(tmp64);
- break;
- case MO_BEQ:
- qemu_st_beq(tmp64);
- break;
- default:
- g_assert_not_reached();
- }
+ tci_qemu_st(env, taddr, tmp64, oi, tb_ptr);
break;
case INDEX_op_mb:
--
2.25.1
- [PATCH v7 19/27] tcg/tci: Implement extract, sextract, (continued)
- [PATCH v7 19/27] tcg/tci: Implement extract, sextract, Richard Henderson, 2021/06/01
- [PATCH v7 17/27] tcg/tci: Implement movcond, Richard Henderson, 2021/06/01
- [PATCH v7 12/27] tcg/tci: Reserve r13 for a temporary, Richard Henderson, 2021/06/01
- [PATCH v7 14/27] tcg/tci: Remove tci_write_reg, Richard Henderson, 2021/06/01
- [PATCH v7 18/27] tcg/tci: Implement andc, orc, eqv, nand, nor, Richard Henderson, 2021/06/01
- [PATCH v7 26/27] tcg/tci: Use {set,clear}_helper_retaddr, Richard Henderson, 2021/06/01
- [PATCH v7 24/27] Revert "tcg/tci: Use exec/cpu_ldst.h interfaces", Richard Henderson, 2021/06/01
- [PATCH v7 23/27] tcg/tci: Split out tci_qemu_ld, tci_qemu_st,
Richard Henderson <=
- [PATCH v7 20/27] tcg/tci: Implement clz, ctz, ctpop, Richard Henderson, 2021/06/01
- Re: [PATCH v7 00/27] TCI fixes and cleanups, no-reply, 2021/06/01
- Re: [PATCH v7 00/27] TCI fixes and cleanups, Philippe Mathieu-Daudé, 2021/06/19