Re: [PATCH] docs/devel: Explain in more detail the TB chaining mechanisms

[Richard Henderson]

On 5/28/21 5:30 AM, Luis Pires wrote:
> +In its simplest, less optimized form, this is done by exiting from the
> +current TB, going through the TB epilogue, and then back to the outer
> +execution loop. That’s where QEMU looks for the next TB to execute,
> +translating it from the guest architecture if it isn’t already available
> +in memory. Then QEMU proceeds to execute this next TB, starting at the
> +prologue and then moving on to the translated instructions.

It is important to mention that by exiting this way, we immediately re-evaluate 
cc->cpu_exec_interrupt().  It is mandatory to exit this way after any cpu state 
change that may unmask interrupts.

This is often referred to as "exit to the main loop" in the translators.  In my 
recent changes to the ppc translator, I introduced DISAS_EXIT* for the purpose.


> +In order to accelerate the most common cases where the TB for the new
> +simulated PC is already available, QEMU has mechanisms that allow
> +multiple TBs to be chained directly, without having to go back to the
> +outer execution loop as described above. These mechanisms are:
> +
> +``lookup_and_goto_ptr``
> +^^^^^^^^^^^^^^^^^^^^^^^
> +
> +On platforms that support the ``lookup_and_goto_ptr`` mechanism, calling
> +``tcg_gen_lookup_and_goto_ptr()`` will emit TCG instructions that call
> +a helper function to look for the destination TB, based on
> +the CPU state information. If the destination TB is available, a
> +``goto_ptr`` TCG instruction is emitted to jump directly to its first
> +instruction, skipping the epilogue - execution loop - prologue path.
> +If the destination TB is not available, the ``goto_ptr`` instruction
> +jumps to the epilogue, effectively exiting from the current TB and
> +going back to the execution loop.

I'm one step shy of making TCG_TARGET_HAS_goto_ptr mandatory, and I don't think 
it's useful to focus on what the fallback mechanisms are.  In particular, 
lookup_and_goto_ptr will exit to the main loop with '-d nochain'.

The timeline is off here as well.  The goto_ptr tcg opcode is not conditionally 
emitted -- it is always emitted.  Better phrasing:

  ... will emit a call to ``helper_lookup_tb_ptr``.  This helper
  will look for an existing TB that matches the current CPU state.
  If the destination TB is available its code address is returned,
  otherwise the address of the JIT epilogue is returned.  The call
  to the helper is always followed by the tcg ``goto_ptr`` opcode,
  which branches to the returned address.  In this way, we either
  branch to the next TB or return to the main loop.


> +On platforms that do not support this mechanism, the
> +``tcg_gen_lookup_and_goto_ptr()`` function will just use
> +``tcg_gen_exit_tb()`` to exit from the current TB.

Just drop this bit.

> +``goto_tb + exit_tb``
> +^^^^^^^^^^^^^^^^^^^^^
> +
> +On platforms that support this mechanism, the translation code usually
> +implements branching by performing the following steps:

Again drop "on platforms that support", because they all do -- it's mandatory.

It's also very important to note when this cannot be used: the change in cpu 
state must be constant.  E.g. a direct branch not an indirect branch.  A 
surprising edge case here in the past has been a direct branch with a 
conditional delay slot nullification.

Moreover, even the direct branch cannot cross a page boundary, because memory 
mappings may change causing the code at the destination address to change.

> +
> +1. Call ``tcg_gen_goto_tb()`` passing a jump slot index (either 0 or 1)
> +   as a parameter
> +
> +2. Emit TCG instructions to update the CPU state information with the
> +   address of the next instruction to execute

More completely, update the CPU state with any information that has been 
assumed constant.  For most guests, this is just the PC.  But e.g. for hppa 
this is both iaoq.f (cip) and iaoq.b (nip).

It is very much up to the guest to determine the set of data that is present in 
cpu_get_tb_cpu_state, and what can be assumed across the break.

> +The first time this whole sequence is translated to target instructions
> +and executed, step 1 doesn’t do anything really useful, as it just jumps
> +to step 2.

Timing problem.  When the whole sequence is translated is immaterial.  You mean 
the first time this sequence is executed.  Drop the "doesn't do anything 
useful" phrase.


> Then the CPU state information gets updated and we exit from
> +the current TB. As a result, the behavior is very similar to the less
> +optimized form described earlier in this section.
> +
> +Next, the execution loop looks for the next TB to execute using the
> +current CPU state information (creating the TB if it wasn’t already
> +available) and, before starting to execute the new TB’s instructions,
> +tries to patch the previously executed TB by associating one of its jump

s/tries to patch/patches/.  There's no failure possible.

> +The most portable code patches TBs using indirect jumps. An indirect
> +jump makes it easier to make the jump target modification atomic. On some
> +host architectures (such as x86 and PowerPC), the ``JUMP`` opcode is

This detail should be elsewhere. This is an internal choice of the tcg backend, 
depending on the host architecture.


r~