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Re: [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option
From: |
Alistair Francis |
Subject: |
Re: [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option |
Date: |
Fri, 28 May 2021 08:05:22 +1000 |
On Thu, May 6, 2021 at 2:27 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Default b-ext version is v0.93.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 23 +++++++++++++++++++++++
> target/riscv/cpu.h | 3 +++
> 2 files changed, 26 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1b3c5ba1480..32469f7c891 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -127,6 +127,11 @@ static void set_priv_version(CPURISCVState *env, int
> priv_ver)
> env->priv_ver = priv_ver;
> }
>
> +static void set_bext_version(CPURISCVState *env, int bext_ver)
> +{
> + env->bext_ver = bext_ver;
> +}
> +
> static void set_vext_version(CPURISCVState *env, int vext_ver)
> {
> env->vext_ver = vext_ver;
> @@ -385,6 +390,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> CPURISCVState *env = &cpu->env;
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> int priv_version = PRIV_VERSION_1_11_0;
> + int bext_version = BEXT_VERSION_0_93_0;
> int vext_version = VEXT_VERSION_0_07_1;
> target_ulong target_misa = env->misa;
> Error *local_err = NULL;
> @@ -409,6 +415,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
>
> set_priv_version(env, priv_version);
> + set_bext_version(env, bext_version);
> set_vext_version(env, vext_version);
>
> if (cpu->cfg.mmu) {
> @@ -488,6 +495,21 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
> if (cpu->cfg.ext_b) {
> target_misa |= RVB;
> +
> + if (cpu->cfg.bext_spec) {
> + if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) {
> + bext_version = BEXT_VERSION_0_93_0;
> + } else {
> + error_setg(errp,
> + "Unsupported bitmanip spec version '%s'",
> + cpu->cfg.bext_spec);
> + return;
> + }
> + } else {
> + qemu_log("bitmanip version is not specified, "
> + "use the default value v0.93\n");
> + }
> + set_bext_version(env, bext_version);
> }
> if (cpu->cfg.ext_v) {
> target_misa |= RVV;
> @@ -566,6 +588,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> + DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3cea62cd4c4..b2cca778526 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -83,6 +83,7 @@ enum {
> #define PRIV_VERSION_1_10_0 0x00011000
> #define PRIV_VERSION_1_11_0 0x00011100
>
> +#define BEXT_VERSION_0_93_0 0x00009300
> #define VEXT_VERSION_0_07_1 0x00000701
>
> enum {
> @@ -130,6 +131,7 @@ struct CPURISCVState {
> target_ulong guest_phys_fault_addr;
>
> target_ulong priv_ver;
> + target_ulong bext_ver;
> target_ulong vext_ver;
> target_ulong misa;
> target_ulong misa_mask;
> @@ -295,6 +297,7 @@ struct RISCVCPU {
>
> char *priv_spec;
> char *user_spec;
> + char *bext_spec;
> char *vext_spec;
> uint16_t vlen;
> uint16_t elen;
> --
> 2.17.1
>
>
- Re: [PATCH v6 09/17] target/riscv: rvb: single-bit instructions, (continued)
- [PATCH v6 10/17] target/riscv: rvb: shift ones, frank . chang, 2021/05/05
- [PATCH v6 11/17] target/riscv: rvb: rotate (left/right), frank . chang, 2021/05/05
- [PATCH v6 12/17] target/riscv: rvb: generalized reverse, frank . chang, 2021/05/05
- [PATCH v6 13/17] target/riscv: rvb: generalized or-combine, frank . chang, 2021/05/05
- [PATCH v6 14/17] target/riscv: rvb: address calculation, frank . chang, 2021/05/05
- [PATCH v6 15/17] target/riscv: rvb: add/shift with prefix zero-extend, frank . chang, 2021/05/05
- [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option, frank . chang, 2021/05/05
- Re: [PATCH v6 17/17] target/riscv: rvb: add b-ext version cpu option,
Alistair Francis <=
- [PATCH v6 16/17] target/riscv: rvb: support and turn on B-extension from command line, frank . chang, 2021/05/05
- Re: [PATCH v6 00/17] support subsets of bitmanip extension, Alistair Francis, 2021/05/27