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[PATCH v7 66/92] target/arm: Implement SVE mixed sign dot product (index
From: |
Richard Henderson |
Subject: |
[PATCH v7 66/92] target/arm: Implement SVE mixed sign dot product (indexed) |
Date: |
Mon, 24 May 2021 18:03:32 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v7: Macroize the helpers.
---
target/arm/cpu.h | 5 +++++
target/arm/helper.h | 4 ++++
target/arm/sve.decode | 4 ++++
target/arm/translate-sve.c | 16 ++++++++++++++++
target/arm/vec_helper.c | 2 ++
5 files changed, 31 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 595bc6349d..0a41142d35 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -4246,6 +4246,11 @@ static inline bool isar_feature_aa64_sve2_bitperm(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
}
+static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
+}
+
static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
diff --git a/target/arm/helper.h b/target/arm/helper.h
index e7c463fff5..e4c6458f98 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -621,6 +621,10 @@ DEF_HELPER_FLAGS_5(gvec_sdot_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_udot_idx_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_sudot_idx_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_usdot_idx_b, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(gvec_fcaddh, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 0339410cf7..c6b32a3f69 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -816,6 +816,10 @@ SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... .....
@rrxr_3 esz=1
SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2
SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3
+# SVE mixed sign dot product (indexed)
+USDOT_zzxw_s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2
+SUDOT_zzxw_s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2
+
# SVE2 saturating multiply-add (indexed)
SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2
SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b454f50a6b..30894a4143 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3838,6 +3838,22 @@ DO_RRXR(trans_SDOT_zzxw_d, gen_helper_gvec_sdot_idx_h)
DO_RRXR(trans_UDOT_zzxw_s, gen_helper_gvec_udot_idx_b)
DO_RRXR(trans_UDOT_zzxw_d, gen_helper_gvec_udot_idx_h)
+static bool trans_SUDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve_i8mm, s)) {
+ return false;
+ }
+ return do_zzxz_ool(s, a, gen_helper_gvec_sudot_idx_b);
+}
+
+static bool trans_USDOT_zzxw_s(DisasContext *s, arg_rrxr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve_i8mm, s)) {
+ return false;
+ }
+ return do_zzxz_ool(s, a, gen_helper_gvec_usdot_idx_b);
+}
+
#undef DO_RRXR
static bool do_sve2_zzz_data(DisasContext *s, int rd, int rn, int rm, int data,
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index 1c4266a9c0..f128b41eac 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -598,6 +598,8 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *va,
uint32_t desc) \
DO_DOT_IDX(gvec_sdot_idx_b, int32_t, int8_t, int8_t, H4)
DO_DOT_IDX(gvec_udot_idx_b, uint32_t, uint8_t, uint8_t, H4)
+DO_DOT_IDX(gvec_sudot_idx_b, int32_t, int8_t, uint8_t, H4)
+DO_DOT_IDX(gvec_usdot_idx_b, int32_t, uint8_t, int8_t, H4)
DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, )
DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, )
--
2.25.1
- [PATCH v7 56/92] target/arm: Implement SVE2 saturating multiply-add (indexed), (continued)
- [PATCH v7 56/92] target/arm: Implement SVE2 saturating multiply-add (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 55/92] target/arm: Implement SVE2 saturating multiply-add high (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 59/92] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 47/92] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2021/05/24
- [PATCH v7 60/92] target/arm: Implement SVE2 multiply-add long (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 68/92] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2021/05/24
- [PATCH v7 52/92] target/arm: Split out formats for 3 vectors + 1 index, Richard Henderson, 2021/05/24
- [PATCH v7 45/92] target/arm: Implement SVE2 gather load insns, Richard Henderson, 2021/05/24
- [PATCH v7 58/92] target/arm: Implement SVE2 signed saturating doubling multiply high, Richard Henderson, 2021/05/24
- [PATCH v7 61/92] target/arm: Implement SVE2 integer multiply long (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 66/92] target/arm: Implement SVE mixed sign dot product (indexed),
Richard Henderson <=
- [PATCH v7 67/92] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2021/05/24
- [PATCH v7 57/92] target/arm: Implement SVE2 saturating multiply (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 50/92] target/arm: Pass separate addend to FCMLA helpers, Richard Henderson, 2021/05/24
- [PATCH v7 70/92] target/arm: Implement SVE2 crypto constructive binary operations, Richard Henderson, 2021/05/24
- [PATCH v7 69/92] target/arm: Implement SVE2 crypto destructive binary operations, Richard Henderson, 2021/05/24
- [PATCH v7 51/92] target/arm: Split out formats for 2 vectors + 1 index, Richard Henderson, 2021/05/24
- [PATCH v7 54/92] target/arm: Implement SVE2 integer multiply-add (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 65/92] target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}, Richard Henderson, 2021/05/24
- [PATCH v7 63/92] target/arm: Implement SVE2 complex integer dot product, Richard Henderson, 2021/05/24
- [PATCH v7 53/92] target/arm: Implement SVE2 integer multiply (indexed), Richard Henderson, 2021/05/24