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Re: [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro
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From: |
Peter Maydell |
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Subject: |
Re: [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro |
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Date: |
Thu, 20 May 2021 14:55:40 +0100 |
On Tue, 11 May 2021 at 11:22, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Message-id:
> fcc125d96da941b56c817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
> ---
> target/riscv/cpu_bits.h | 10 ----------
> target/riscv/csr.c | 12 ++++++++++--
> target/riscv/translate.c | 19 +++++++++++++++++--
> 3 files changed, 27 insertions(+), 14 deletions(-)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 26eccc5eb1..a596f80f20 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> return ctx->misa & ext;
> }
>
> +#ifdef TARGET_RISCV32
> +# define is_32bit(ctx) true
> +#elif defined(CONFIG_USER_ONLY)
> +# define is_32bit(ctx) false
> +#else
> +static inline bool is_32bit(DisasContext *ctx)
> +{
> + return (ctx->misa & RV32) == RV32;
> +}
> +#endif
Hi; Coverity points out (CID 1453107) that this is_32bit() function
can never return true for at least some build configs, because RV32
is defined as ((target_ulong)1 << (TARGET_LONG_BITS - 2))
but ctx->misa is a uint32_t field, which (if TARGET_LONG_BITS is
64) is not big enough for the RV32 bit.
Bug, or false positive ?
thanks
-- PMM
- [PULL v3 27/42] target/riscv: Add ePMP support for the Ibex CPU, (continued)
- [PULL v3 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/11
- [PULL v3 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/11
- [PULL v3 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/11
- [PULL v3 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/11
- [PULL v3 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/11
- [PULL v3 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/11
- [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/11
- [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/11
- [PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/11
- [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/11
- Re: [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro,
Peter Maydell <=
[PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/11
[PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/11
[PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/11
[PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/11
[PULL v3 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/11
[PULL v3 42/42] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/05/11
Re: [PULL v3 00/42] riscv-to-apply queue, Peter Maydell, 2021/05/12