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[PULL 15/48] target/ppc: moved ppc_cpu_dump_state to cpu_init.c
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From: |
David Gibson |
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Subject: |
[PULL 15/48] target/ppc: moved ppc_cpu_dump_state to cpu_init.c |
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Date: |
Wed, 19 May 2021 22:51:15 +1000 |
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>
This function was forgotten in the cpu_init code motion series, but it
seems to be used regardless of TCG, and so needs to be moved to support
disabling TCG.
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Message-Id: <20210512140813.112884-4-bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu_init.c | 182 +++++++++++++++++++++++++++++++++++++++
target/ppc/translate.c | 187 -----------------------------------------
2 files changed, 182 insertions(+), 187 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 022fa69d2c..22ecbccad8 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -9368,4 +9368,186 @@ static void ppc_cpu_register_types(void)
#endif
}
+void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+{
+#define RGPL 4
+#define RFPL 4
+
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+ int i;
+
+ qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
+ TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
+ env->nip, env->lr, env->ctr, cpu_read_xer(env),
+ cs->cpu_index);
+ qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
+ "%08x iidx %d didx %d\n",
+ env->msr, env->spr[SPR_HID0], env->hflags,
+ cpu_mmu_index(env, true), cpu_mmu_index(env, false));
+#if !defined(NO_TIMER_DUMP)
+ qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
+#if !defined(CONFIG_USER_ONLY)
+ " DECR " TARGET_FMT_lu
+#endif
+ "\n",
+ cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
+#if !defined(CONFIG_USER_ONLY)
+ , cpu_ppc_load_decr(env)
+#endif
+ );
+#endif
+ for (i = 0; i < 32; i++) {
+ if ((i & (RGPL - 1)) == 0) {
+ qemu_fprintf(f, "GPR%02d", i);
+ }
+ qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
+ if ((i & (RGPL - 1)) == (RGPL - 1)) {
+ qemu_fprintf(f, "\n");
+ }
+ }
+ qemu_fprintf(f, "CR ");
+ for (i = 0; i < 8; i++)
+ qemu_fprintf(f, "%01x", env->crf[i]);
+ qemu_fprintf(f, " [");
+ for (i = 0; i < 8; i++) {
+ char a = '-';
+ if (env->crf[i] & 0x08) {
+ a = 'L';
+ } else if (env->crf[i] & 0x04) {
+ a = 'G';
+ } else if (env->crf[i] & 0x02) {
+ a = 'E';
+ }
+ qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
+ }
+ qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
+ env->reserve_addr);
+
+ if (flags & CPU_DUMP_FPU) {
+ for (i = 0; i < 32; i++) {
+ if ((i & (RFPL - 1)) == 0) {
+ qemu_fprintf(f, "FPR%02d", i);
+ }
+ qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
+ if ((i & (RFPL - 1)) == (RFPL - 1)) {
+ qemu_fprintf(f, "\n");
+ }
+ }
+ qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
+ }
+
+#if !defined(CONFIG_USER_ONLY)
+ qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
+ " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
+ env->spr[SPR_SRR0], env->spr[SPR_SRR1],
+ env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
+
+ qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
+ " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
+ env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
+ env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
+
+ qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
+ " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
+ env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
+ env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
+
+#if defined(TARGET_PPC64)
+ if (env->excp_model == POWERPC_EXCP_POWER7 ||
+ env->excp_model == POWERPC_EXCP_POWER8 ||
+ env->excp_model == POWERPC_EXCP_POWER9 ||
+ env->excp_model == POWERPC_EXCP_POWER10) {
+ qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
+ env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
+ }
+#endif
+ if (env->excp_model == POWERPC_EXCP_BOOKE) {
+ qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
+ " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
+ env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
+ env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
+
+ qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
+ " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
+ env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
+ env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
+
+ qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
+ " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
+ env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
+ env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
+
+ qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
+ " EPR " TARGET_FMT_lx "\n",
+ env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
+ env->spr[SPR_BOOKE_EPR]);
+
+ /* FSL-specific */
+ qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
+ " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
+ env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
+ env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
+
+ /*
+ * IVORs are left out as they are large and do not change often --
+ * they can be read with "p $ivor0", "p $ivor1", etc.
+ */
+ }
+
+#if defined(TARGET_PPC64)
+ if (env->flags & POWERPC_FLAG_CFAR) {
+ qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
+ }
+#endif
+
+ if (env->spr_cb[SPR_LPCR].name) {
+ qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
+ }
+
+ switch (env->mmu_model) {
+ case POWERPC_MMU_32B:
+ case POWERPC_MMU_601:
+ case POWERPC_MMU_SOFT_6xx:
+ case POWERPC_MMU_SOFT_74xx:
+#if defined(TARGET_PPC64)
+ case POWERPC_MMU_64B:
+ case POWERPC_MMU_2_03:
+ case POWERPC_MMU_2_06:
+ case POWERPC_MMU_2_07:
+ case POWERPC_MMU_3_00:
+#endif
+ if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
+ qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
+ }
+ if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
+ qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
+ }
+ qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
+ env->spr[SPR_DAR], env->spr[SPR_DSISR]);
+ break;
+ case POWERPC_MMU_BOOKE206:
+ qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
+ " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
+ env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
+ env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
+
+ qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
+ " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
+ env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
+ env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
+
+ qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
+ " TLB1CFG " TARGET_FMT_lx "\n",
+ env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
+ env->spr[SPR_BOOKE_TLB1CFG]);
+ break;
+ default:
+ break;
+ }
+#endif
+
+#undef RGPL
+#undef RFPL
+}
type_init(ppc_cpu_register_types)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 5e3495e018..6c68d7006a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -8617,193 +8617,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F,
0x03FFF800, \
#include "translate/spe-ops.c.inc"
};
-#include "helper_regs.h"
-
-/*****************************************************************************/
-/* Misc PowerPC helpers */
-void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
-{
-#define RGPL 4
-#define RFPL 4
-
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- CPUPPCState *env = &cpu->env;
- int i;
-
- qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
- TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
- env->nip, env->lr, env->ctr, cpu_read_xer(env),
- cs->cpu_index);
- qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
- "%08x iidx %d didx %d\n",
- env->msr, env->spr[SPR_HID0], env->hflags,
- cpu_mmu_index(env, true), cpu_mmu_index(env, false));
-#if !defined(NO_TIMER_DUMP)
- qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
-#if !defined(CONFIG_USER_ONLY)
- " DECR " TARGET_FMT_lu
-#endif
- "\n",
- cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
-#if !defined(CONFIG_USER_ONLY)
- , cpu_ppc_load_decr(env)
-#endif
- );
-#endif
- for (i = 0; i < 32; i++) {
- if ((i & (RGPL - 1)) == 0) {
- qemu_fprintf(f, "GPR%02d", i);
- }
- qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
- if ((i & (RGPL - 1)) == (RGPL - 1)) {
- qemu_fprintf(f, "\n");
- }
- }
- qemu_fprintf(f, "CR ");
- for (i = 0; i < 8; i++)
- qemu_fprintf(f, "%01x", env->crf[i]);
- qemu_fprintf(f, " [");
- for (i = 0; i < 8; i++) {
- char a = '-';
- if (env->crf[i] & 0x08) {
- a = 'L';
- } else if (env->crf[i] & 0x04) {
- a = 'G';
- } else if (env->crf[i] & 0x02) {
- a = 'E';
- }
- qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
- }
- qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
- env->reserve_addr);
-
- if (flags & CPU_DUMP_FPU) {
- for (i = 0; i < 32; i++) {
- if ((i & (RFPL - 1)) == 0) {
- qemu_fprintf(f, "FPR%02d", i);
- }
- qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
- if ((i & (RFPL - 1)) == (RFPL - 1)) {
- qemu_fprintf(f, "\n");
- }
- }
- qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
- }
-
-#if !defined(CONFIG_USER_ONLY)
- qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
- " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
- env->spr[SPR_SRR0], env->spr[SPR_SRR1],
- env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
-
- qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
- " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
- env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
- env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
-
- qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
- " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
- env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
- env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
-
-#if defined(TARGET_PPC64)
- if (env->excp_model == POWERPC_EXCP_POWER7 ||
- env->excp_model == POWERPC_EXCP_POWER8 ||
- env->excp_model == POWERPC_EXCP_POWER9 ||
- env->excp_model == POWERPC_EXCP_POWER10) {
- qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
- env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
- }
-#endif
- if (env->excp_model == POWERPC_EXCP_BOOKE) {
- qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
- " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
- env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
-
- qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
- " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
- env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
-
- qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
- " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
- env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
-
- qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
- " EPR " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
- env->spr[SPR_BOOKE_EPR]);
-
- /* FSL-specific */
- qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
- " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
- env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
- env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
-
- /*
- * IVORs are left out as they are large and do not change often --
- * they can be read with "p $ivor0", "p $ivor1", etc.
- */
- }
-
-#if defined(TARGET_PPC64)
- if (env->flags & POWERPC_FLAG_CFAR) {
- qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
- }
-#endif
-
- if (env->spr_cb[SPR_LPCR].name) {
- qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
- }
-
- switch (env->mmu_model) {
- case POWERPC_MMU_32B:
- case POWERPC_MMU_601:
- case POWERPC_MMU_SOFT_6xx:
- case POWERPC_MMU_SOFT_74xx:
-#if defined(TARGET_PPC64)
- case POWERPC_MMU_64B:
- case POWERPC_MMU_2_03:
- case POWERPC_MMU_2_06:
- case POWERPC_MMU_2_07:
- case POWERPC_MMU_3_00:
-#endif
- if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
- qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
- }
- if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
- qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
- }
- qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
- env->spr[SPR_DAR], env->spr[SPR_DSISR]);
- break;
- case POWERPC_MMU_BOOKE206:
- qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
- " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
- env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
-
- qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
- " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
- env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
- env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
-
- qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
- " TLB1CFG " TARGET_FMT_lx "\n",
- env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
- env->spr[SPR_BOOKE_TLB1CFG]);
- break;
- default:
- break;
- }
-#endif
-
-#undef RGPL
-#undef RFPL
-}
-
/*****************************************************************************/
/* Opcode types */
enum {
--
2.31.1
- [PULL 02/48] hw/ppc/spapr.c: Make sure the host supports the selected MMU mode, (continued)
- [PULL 02/48] hw/ppc/spapr.c: Make sure the host supports the selected MMU mode, David Gibson, 2021/05/19
- [PULL 03/48] target/ppc: Fold gen_*_xer into their callers, David Gibson, 2021/05/19
- [PULL 01/48] hw/ppc/spapr.c: Extract MMU mode error reporting into a function, David Gibson, 2021/05/19
- [PULL 04/48] target/ppc: renamed SPR registration functions, David Gibson, 2021/05/19
- [PULL 08/48] target/ppc: moved ppc_store_lpcr to misc_helper.c, David Gibson, 2021/05/19
- [PULL 10/48] target/ppc: turned SPR R/W callbacks not static, David Gibson, 2021/05/19
- [PULL 07/48] target/ppc: moved function out of mmu-hash64, David Gibson, 2021/05/19
- [PULL 09/48] hw/ppc: moved has_spr to cpu.h, David Gibson, 2021/05/19
- [PULL 12/48] target/ppc: created ppc_{store, get}_vscr for generic vscr usage, David Gibson, 2021/05/19
- [PULL 11/48] target/ppc: isolated cpu init from translation logic, David Gibson, 2021/05/19
- [PULL 15/48] target/ppc: moved ppc_cpu_dump_state to cpu_init.c,
David Gibson <=
- [PULL 20/48] target/ppc: Remove special case for POWERPC_EXCP_TRAP, David Gibson, 2021/05/19
- [PULL 06/48] hw/ppc: moved hcalls that depend on softmmu, David Gibson, 2021/05/19
- [PULL 05/48] target/ppc: move SPR R/W callbacks to translate.c, David Gibson, 2021/05/19
- [PULL 21/48] target/ppc: Simplify gen_debug_exception, David Gibson, 2021/05/19
- [PULL 22/48] target/ppc: Introduce DISAS_{EXIT,CHAIN}{,_UPDATE}, David Gibson, 2021/05/19
- [PULL 17/48] target/ppc: Split out decode_legacy, David Gibson, 2021/05/19
- [PULL 16/48] target/ppc: Add cia field to DisasContext, David Gibson, 2021/05/19
- [PULL 14/48] target/ppc: moved ppc_store_sdr1 to cpu.c, David Gibson, 2021/05/19
- [PULL 13/48] target/ppc: updated vscr manipulation in machine.c, David Gibson, 2021/05/19
- [PULL 18/48] target/ppc: Move DISAS_NORETURN setting into gen_exception*, David Gibson, 2021/05/19