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Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
From: |
David Gibson |
Subject: |
Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree |
Date: |
Tue, 18 May 2021 10:56:36 +1000 |
On Mon, May 17, 2021 at 05:50:25PM -0300, matheus.ferst@eldorado.org.br wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/insn32.decode | 14 ++++++
> target/ppc/translate.c | 52 ----------------------
> target/ppc/translate/fixedpoint-impl.c.inc | 31 +++++++++++++
> 3 files changed, 45 insertions(+), 52 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 93e5d44d9e..9fd8d6b817 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -20,6 +20,10 @@
> &D rt ra si:int64_t
> @D ...... rt:5 ra:5 si:s16 &D
>
> +&D_bf bf l:bool ra imm
> +@D_bfs ...... bf:3 - l:1 ra:5 imm:s16 &D_bf
> +@D_bfu ...... bf:3 - l:1 ra:5 imm:16 &D_bf
> +
> %ds_si 2:s14 !function=times_4
> @DS ...... rt:5 ra:5 .............. .. &D si=%ds_si
>
> @@ -36,6 +40,9 @@
> &X_bi rt bi
> @X_bi ...... rt:5 bi:5 ----- .......... - &X_bi
>
> +&X_bfl bf l:bool ra rb
> +@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
> +
> ### Fixed-Point Load Instructions
>
> LBZ 100010 ..... ..... ................ @D
> @@ -89,6 +96,13 @@ STDU 111110 ..... ..... ..............01 @DS
> STDX 011111 ..... ..... ..... 0010010101 - @X
> STDUX 011111 ..... ..... ..... 0010110101 - @X
>
> +### Fixed-Point Compare Instructions
> +
> +CMP 011111 ... - . ..... ..... 0000000000 - @X_bfl
> +CMPL 011111 ... - . ..... ..... 0000100000 - @X_bfl
> +CMPI 001011 ... - . ..... ................ @D_bfs
> +CMPLI 001010 ... - . ..... ................ @D_bfu
> +
> ### Fixed-Point Arithmetic Instructions
>
> ADDI 001110 ..... ..... ................ @D
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index aef01af396..3fe58d0386 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -1575,54 +1575,6 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv
> reg)
> }
> }
>
> -/* cmp */
> -static void gen_cmp(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 1, crfD(ctx->opcode));
> - } else {
> - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 1, crfD(ctx->opcode));
> - }
> -}
> -
> -/* cmpi */
> -static void gen_cmpi(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
> - 1, crfD(ctx->opcode));
> - } else {
> - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
> - 1, crfD(ctx->opcode));
> - }
> -}
> -
> -/* cmpl */
> -static void gen_cmpl(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 0, crfD(ctx->opcode));
> - } else {
> - gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
> - 0, crfD(ctx->opcode));
> - }
> -}
> -
> -/* cmpli */
> -static void gen_cmpli(DisasContext *ctx)
> -{
> - if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
> - gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
> - 0, crfD(ctx->opcode));
> - } else {
> - gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
> - 0, crfD(ctx->opcode));
> - }
> -}
> -
> /* cmprb - range comparison: isupper, isaplha, islower*/
> static void gen_cmprb(DisasContext *ctx)
> {
> @@ -7725,10 +7677,6 @@ GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801,
> PPC_NONE, PPC2_ISA310),
> GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
> #endif
> GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
> -GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
> -GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
> -GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER),
> -GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
> #if defined(TARGET_PPC64)
> GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300),
> #endif
> diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
> b/target/ppc/translate/fixedpoint-impl.c.inc
> index 4f257a931c..49c8993333 100644
> --- a/target/ppc/translate/fixedpoint-impl.c.inc
> +++ b/target/ppc/translate/fixedpoint-impl.c.inc
> @@ -165,6 +165,37 @@ TRANS64(STDU, do_ldst_D, true, true, MO_Q)
> TRANS64(STDUX, do_ldst_X, true, true, MO_Q)
> TRANS64(PSTD, do_ldst_PLS_D, false, true, MO_Q)
>
> +/*
> + * Fixed-Point Compare Instructions
> + */
> +
> +static bool do_cmp_X(DisasContext *ctx, arg_X_bfl *a, bool s)
> +{
> + REQUIRE_INSNS_FLAGS(ctx, INTEGER);
> + if(a->l && (ctx->insns_flags & PPC_64B)) {
> + gen_op_cmp(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
> + } else {
> + gen_op_cmp32(cpu_gpr[a->ra], cpu_gpr[a->rb], s, a->bf);
> + }
> + return true;
> +}
> +
> +static bool do_cmp_D(DisasContext *ctx, arg_D_bf *a, bool s)
> +{
> + REQUIRE_INSNS_FLAGS(ctx, INTEGER);
> + if(a->l && (ctx->insns_flags & PPC_64B)) {
> + gen_op_cmp(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
> + } else {
> + gen_op_cmp32(cpu_gpr[a->ra], tcg_constant_tl(a->imm), s, a->bf);
> + }
> + return true;
> +}
> +
> +TRANS(CMP, do_cmp_X, true);
> +TRANS(CMPL, do_cmp_X, false);
> +TRANS(CMPI, do_cmp_D, true);
> +TRANS(CMPLI, do_cmp_D, false);
> +
> /*
> * Fixed-Point Arithmetic Instructions
> */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions, (continued)
- [PATCH v5 20/23] target/ppc: Implement cfuged instruction, matheus . ferst, 2021/05/17
- [PATCH v5 21/23] target/ppc: Implement vcfuged instruction, matheus . ferst, 2021/05/17
- [PATCH v5 22/23] target/ppc: Move addpcis to decodetree, matheus . ferst, 2021/05/17
- [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, matheus . ferst, 2021/05/17
- Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree,
David Gibson <=
- Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, Richard Henderson, 2021/05/18
- Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, Matheus K. Ferst, 2021/05/21
- Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, Richard Henderson, 2021/05/24
- Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, Matheus K. Ferst, 2021/05/26
- Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, Richard Henderson, 2021/05/26
- Re: [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, David Gibson, 2021/05/26
Re: [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions, David Gibson, 2021/05/18