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[PULL v3 42/42] target/riscv: Fix the RV64H decode comment
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From: |
Alistair Francis |
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Subject: |
[PULL v3 42/42] target/riscv: Fix the RV64H decode comment |
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Date: |
Tue, 11 May 2021 20:19:51 +1000 |
BugLink: https://gitlab.com/qemu-project/qemu/-/issues/47
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
024ce841221c1d15c74b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index fecf0f15d5..8901ba1e1b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -288,7 +288,7 @@ hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
-# *** RV32H Base Instruction Set ***
+# *** RV64H Base Instruction Set ***
hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
--
2.31.1
- [PULL v3 32/42] target/riscv: fix a typo with interrupt names, (continued)
- [PULL v3 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/11
- [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/11
- [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/11
- [PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/11
- [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/11
- [PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/11
- [PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/11
- [PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/11
- [PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/11
- [PULL v3 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/11
- [PULL v3 42/42] target/riscv: Fix the RV64H decode comment,
Alistair Francis <=
- Re: [PULL v3 00/42] riscv-to-apply queue, Peter Maydell, 2021/05/12