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[PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
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From: |
Alistair Francis |
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Subject: |
[PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine |
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Date: |
Tue, 11 May 2021 20:19:25 +1000 |
imply VIRTIO_VGA for the virt machine, this fixes the following error
when specifying `-vga virtio` as a command line argument:
qemu-system-riscv64: Virtio VGA not available
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
7ac26fafee8bd59d2a0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com
---
hw/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index a0225716b5..86957ec7b0 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -32,6 +32,7 @@ config SHAKTI_C
config RISCV_VIRT
bool
imply PCI_DEVICES
+ imply VIRTIO_VGA
imply TEST_DEVICES
select GOLDFISH_RTC
select MSI_NONBROKEN
--
2.31.1
- [PULL v3 05/42] target/riscv: Add Shakti C class CPU, (continued)
- [PULL v3 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/11
- [PULL v3 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/11
- [PULL v3 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/11
- [PULL v3 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/11
- [PULL v3 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/11
- [PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/11
- [PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access, Alistair Francis, 2021/05/11
- [PULL v3 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/11
- [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/11
- [PULL v3 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/11
- [PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine,
Alistair Francis <=
- [PULL v3 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/11
- [PULL v3 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/11
- [PULL v3 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/11
- [PULL v3 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/11
- [PULL v3 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/11
- [PULL v3 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/11
- [PULL v3 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/11
- [PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/11