[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access
|
From: |
Alistair Francis |
|
Subject: |
[PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access |
|
Date: |
Tue, 11 May 2021 20:19:22 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
302b208f40373557fa11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
---
target/riscv/cpu.h | 11 +++++++----
target/riscv/csr.c | 37 ++++++++++++++++++-------------------
target/riscv/gdbstub.c | 8 ++++----
target/riscv/op_helper.c | 18 +++++++++---------
4 files changed, 38 insertions(+), 36 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a7b8876ea0..842d3ab810 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -454,10 +454,13 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
*env, target_ulong *pc,
*pflags = flags;
}
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask);
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask);
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask);
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value,
+ target_ulong write_mask);
static inline void riscv_csr_write(CPURISCVState *env, int csrno,
target_ulong val)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f67eaf4042..f0a74f0eb8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1382,10 +1382,11 @@ static RISCVException write_pmpaddr(CPURISCVState *env,
int csrno,
* csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
*/
-int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask)
+RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value, target_ulong write_mask)
{
- int ret;
+ RISCVException ret;
target_ulong old_value;
RISCVCPU *cpu = env_archcpu(env);
@@ -1407,41 +1408,37 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
if ((write_mask && read_only) ||
(!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
- return -RISCV_EXCP_ILLEGAL_INST;
+ return RISCV_EXCP_ILLEGAL_INST;
}
#endif
/* ensure the CSR extension is enabled. */
if (!cpu->cfg.ext_icsr) {
- return -RISCV_EXCP_ILLEGAL_INST;
+ return RISCV_EXCP_ILLEGAL_INST;
}
/* check predicate */
if (!csr_ops[csrno].predicate) {
- return -RISCV_EXCP_ILLEGAL_INST;
+ return RISCV_EXCP_ILLEGAL_INST;
}
ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) {
- return -ret;
+ return ret;
}
/* execute combined read/write operation if it exists */
if (csr_ops[csrno].op) {
- ret = csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
- if (ret != RISCV_EXCP_NONE) {
- return -ret;
- }
- return 0;
+ return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
}
/* if no accessor exists then return failure */
if (!csr_ops[csrno].read) {
- return -RISCV_EXCP_ILLEGAL_INST;
+ return RISCV_EXCP_ILLEGAL_INST;
}
/* read old value */
ret = csr_ops[csrno].read(env, csrno, &old_value);
if (ret != RISCV_EXCP_NONE) {
- return -ret;
+ return ret;
}
/* write value if writable and write mask set, otherwise drop writes */
@@ -1450,7 +1447,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
if (csr_ops[csrno].write) {
ret = csr_ops[csrno].write(env, csrno, new_value);
if (ret != RISCV_EXCP_NONE) {
- return -ret;
+ return ret;
}
}
}
@@ -1460,17 +1457,19 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
*ret_value = old_value;
}
- return 0;
+ return RISCV_EXCP_NONE;
}
/*
* Debugger support. If not in user mode, set env->debugger before the
* riscv_csrrw call and clear it after the call.
*/
-int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
- target_ulong new_value, target_ulong write_mask)
+RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
+ target_ulong *ret_value,
+ target_ulong new_value,
+ target_ulong write_mask)
{
- int ret;
+ RISCVException ret;
#if !defined(CONFIG_USER_ONLY)
env->debugger = true;
#endif
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 5f96b7ea2a..ca78682cf4 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -71,7 +71,7 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray
*buf, int n)
*/
result = riscv_csrrw_debug(env, n - 32, &val,
0, 0);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return gdb_get_regl(buf, val);
}
}
@@ -94,7 +94,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t
*mem_buf, int n)
*/
result = riscv_csrrw_debug(env, n - 32, NULL,
val, -1);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return sizeof(target_ulong);
}
}
@@ -108,7 +108,7 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray
*buf, int n)
int result;
result = riscv_csrrw_debug(env, n, &val, 0, 0);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return gdb_get_regl(buf, val);
}
}
@@ -122,7 +122,7 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t
*mem_buf, int n)
int result;
result = riscv_csrrw_debug(env, n, NULL, val, -1);
- if (result == 0) {
+ if (result == RISCV_EXCP_NONE) {
return sizeof(target_ulong);
}
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index f0bbd73ca5..170b494227 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -41,10 +41,10 @@ target_ulong helper_csrrw(CPURISCVState *env, target_ulong
src,
target_ulong csr)
{
target_ulong val = 0;
- int ret = riscv_csrrw(env, csr, &val, src, -1);
+ RISCVException ret = riscv_csrrw(env, csr, &val, src, -1);
- if (ret < 0) {
- riscv_raise_exception(env, -ret, GETPC());
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
}
return val;
}
@@ -53,10 +53,10 @@ target_ulong helper_csrrs(CPURISCVState *env, target_ulong
src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- int ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
+ RISCVException ret = riscv_csrrw(env, csr, &val, -1, rs1_pass ? src : 0);
- if (ret < 0) {
- riscv_raise_exception(env, -ret, GETPC());
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
}
return val;
}
@@ -65,10 +65,10 @@ target_ulong helper_csrrc(CPURISCVState *env, target_ulong
src,
target_ulong csr, target_ulong rs1_pass)
{
target_ulong val = 0;
- int ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
+ RISCVException ret = riscv_csrrw(env, csr, &val, 0, rs1_pass ? src : 0);
- if (ret < 0) {
- riscv_raise_exception(env, -ret, GETPC());
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
}
return val;
}
--
2.31.1
- [PULL v3 02/42] docs/system/generic-loader.rst: Fix style, (continued)
- [PULL v3 02/42] docs/system/generic-loader.rst: Fix style, Alistair Francis, 2021/05/11
- [PULL v3 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[], Alistair Francis, 2021/05/11
- [PULL v3 03/42] target/riscv: Align the data type of reset vector address, Alistair Francis, 2021/05/11
- [PULL v3 06/42] riscv: Add initial support for Shakti C machine, Alistair Francis, 2021/05/11
- [PULL v3 05/42] target/riscv: Add Shakti C class CPU, Alistair Francis, 2021/05/11
- [PULL v3 11/42] target/riscv: Fix 32-bit HS mode access permissions, Alistair Francis, 2021/05/11
- [PULL v3 07/42] hw/char: Add Shakti UART emulation, Alistair Francis, 2021/05/11
- [PULL v3 08/42] hw/riscv: Connect Shakti UART to Shakti platform, Alistair Francis, 2021/05/11
- [PULL v3 10/42] target/riscv: Use the RISCVException enum for CSR predicates, Alistair Francis, 2021/05/11
- [PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an enum, Alistair Francis, 2021/05/11
- [PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access,
Alistair Francis <=
- [PULL v3 12/42] target/riscv: Use the RISCVException enum for CSR operations, Alistair Francis, 2021/05/11
- [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers, Alistair Francis, 2021/05/11
- [PULL v3 15/42] hw/opentitan: Update the interrupt layout, Alistair Francis, 2021/05/11
- [PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine, Alistair Francis, 2021/05/11
- [PULL v3 17/42] riscv: don't look at SUM when accessing memory from a debugger context, Alistair Francis, 2021/05/11
- [PULL v3 19/42] docs: Add documentation for shakti_c machine, Alistair Francis, 2021/05/11
- [PULL v3 18/42] target/riscv: Fixup saturate subtract function, Alistair Francis, 2021/05/11
- [PULL v3 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/11
- [PULL v3 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/11
- [PULL v3 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/11