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[PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector
From: |
Alistair Francis |
Subject: |
[PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector |
Date: |
Thu, 6 May 2021 09:23:00 +1000 |
From: Alexander Wagner <alexander.wagner@ulal.de>
The IBEX documentation [1] specifies the reset vector to be "the most
significant 3 bytes of the boot address and the reset value (0x80) as
the least significant byte".
[1]
https://github.com/lowRISC/ibex/blob/master/doc/03_reference/exception_interrupts.rst
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420080008.119798-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/opentitan.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 557d73726b..7545dcda9c 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -119,7 +119,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc,
Error **errp)
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
- object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090,
&error_abort);
+ object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080,
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
/* Boot ROM */
--
2.31.1
- [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR, (continued)
- [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/05/05
- [PULL v2 21/42] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/05/05
- [PULL v2 22/42] target/riscv: Add the ePMP feature, Alistair Francis, 2021/05/05
- [PULL v2 23/42] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/05/05
- [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/05/05
- [PULL v2 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/05
- [PULL v2 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/05
- [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/05
- [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/05
- [PULL v2 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/05
- [PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector,
Alistair Francis <=
- [PULL v2 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/05
- [PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/05
- [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/05/05
- [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/05
- [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/05
- [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/05
- [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/05
- [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/05
- [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/05
- [PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/05