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[PATCH v6 05/17] target/riscv: rvb: pack two words into one register
From: |
frank . chang |
Subject: |
[PATCH v6 05/17] target/riscv: rvb: pack two words into one register |
Date: |
Thu, 6 May 2021 00:06:06 +0800 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 6 ++++
target/riscv/insn_trans/trans_rvb.c.inc | 32 ++++++++++++++++++++
target/riscv/translate.c | 40 +++++++++++++++++++++++++
3 files changed, 78 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a4d95ea6217..9b2fd4b6fe8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -666,8 +666,14 @@ cpop 011000 000010 ..... 001 ..... 0010011 @r2
andn 0100000 .......... 111 ..... 0110011 @r
orn 0100000 .......... 110 ..... 0110011 @r
xnor 0100000 .......... 100 ..... 0110011 @r
+pack 0000100 .......... 100 ..... 0110011 @r
+packu 0100100 .......... 100 ..... 0110011 @r
+packh 0000100 .......... 111 ..... 0110011 @r
# *** RV64B Standard Extension (in addition to RV32B) ***
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
+
+packw 0000100 .......... 100 ..... 0111011 @r
+packuw 0100100 .......... 100 ..... 0111011 @r
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index b8676785c6f..770205f96f7 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -53,6 +53,24 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
return gen_arith(ctx, a, tcg_gen_eqv_tl);
}
+static bool trans_pack(DisasContext *ctx, arg_pack *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_pack);
+}
+
+static bool trans_packu(DisasContext *ctx, arg_packu *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packu);
+}
+
+static bool trans_packh(DisasContext *ctx, arg_packh *a)
+{
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packh);
+}
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -73,3 +91,17 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
REQUIRE_EXT(ctx, RVB);
return gen_unary(ctx, a, gen_cpopw);
}
+
+static bool trans_packw(DisasContext *ctx, arg_packw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packw);
+}
+
+static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_EXT(ctx, RVB);
+ return gen_arith(ctx, a, gen_packuw);
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c1a30c21723..5f1a3c694fe 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -548,6 +548,29 @@ static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a,
return true;
}
+static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ tcg_gen_deposit_tl(ret, arg1, arg2,
+ TARGET_LONG_BITS / 2,
+ TARGET_LONG_BITS / 2);
+}
+
+static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
+ tcg_temp_free(t);
+}
+
+static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext8u_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
+ tcg_temp_free(t);
+}
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -567,6 +590,23 @@ static void gen_cpopw(TCGv ret, TCGv arg1)
tcg_gen_ctpop_tl(ret, arg1);
}
+static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_ext16s_tl(t, arg2);
+ tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
+ tcg_temp_free(t);
+}
+
+static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shri_tl(t, arg1, 16);
+ tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
+ tcg_gen_ext32s_tl(ret, ret);
+ tcg_temp_free(t);
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
--
2.17.1
- [PATCH v6 00/17] support subsets of bitmanip extension, frank . chang, 2021/05/05
- [PATCH v6 01/17] target/riscv: reformat @sh format encoding for B-extension, frank . chang, 2021/05/05
- [PATCH v6 03/17] target/riscv: rvb: count bits set, frank . chang, 2021/05/05
- [PATCH v6 02/17] target/riscv: rvb: count leading/trailing zeros, frank . chang, 2021/05/05
- [PATCH v6 05/17] target/riscv: rvb: pack two words into one register,
frank . chang <=
- [PATCH v6 04/17] target/riscv: rvb: logic-with-negate, frank . chang, 2021/05/05
- [PATCH v6 06/17] target/riscv: rvb: min/max instructions, frank . chang, 2021/05/05
- [PATCH v6 07/17] target/riscv: rvb: sign-extend instructions, frank . chang, 2021/05/05
- [PATCH v6 08/17] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, frank . chang, 2021/05/05
- [PATCH v6 09/17] target/riscv: rvb: single-bit instructions, frank . chang, 2021/05/05
- [PATCH v6 10/17] target/riscv: rvb: shift ones, frank . chang, 2021/05/05
- [PATCH v6 11/17] target/riscv: rvb: rotate (left/right), frank . chang, 2021/05/05