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[PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers
From: |
Bruno Larsen (billionai) |
Subject: |
[PATCH v4 1/5] target/ppc: Fold gen_*_xer into their callers |
Date: |
Tue, 4 May 2021 11:01:53 -0300 |
folded gen_{read,write}_xer into their only callers, spr_{read,write}_xer
Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/translate.c | 37 ---------------------------------
target/ppc/translate_init.c.inc | 33 +++++++++++++++++++++++++++--
2 files changed, 31 insertions(+), 39 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b319d409c6..2f10aa2fea 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4175,43 +4175,6 @@ static void gen_tdi(DisasContext *ctx)
/*** Processor control ***/
-static void gen_read_xer(DisasContext *ctx, TCGv dst)
-{
- TCGv t0 = tcg_temp_new();
- TCGv t1 = tcg_temp_new();
- TCGv t2 = tcg_temp_new();
- tcg_gen_mov_tl(dst, cpu_xer);
- tcg_gen_shli_tl(t0, cpu_so, XER_SO);
- tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
- tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
- tcg_gen_or_tl(t0, t0, t1);
- tcg_gen_or_tl(dst, dst, t2);
- tcg_gen_or_tl(dst, dst, t0);
- if (is_isa300(ctx)) {
- tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
- tcg_gen_or_tl(dst, dst, t0);
- tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
- tcg_gen_or_tl(dst, dst, t0);
- }
- tcg_temp_free(t0);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
-}
-
-static void gen_write_xer(TCGv src)
-{
- /* Write all flags, while reading back check for isa300 */
- tcg_gen_andi_tl(cpu_xer, src,
- ~((1u << XER_SO) |
- (1u << XER_OV) | (1u << XER_OV32) |
- (1u << XER_CA) | (1u << XER_CA32)));
- tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
- tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
- tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
- tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
- tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
-}
-
/* mcrxr */
static void gen_mcrxr(DisasContext *ctx)
{
diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc
index d10d7e5bf6..d5527c149f 100644
--- a/target/ppc/translate_init.c.inc
+++ b/target/ppc/translate_init.c.inc
@@ -116,12 +116,41 @@ static void spr_access_nop(DisasContext *ctx, int sprn,
int gprn)
/* XER */
static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
{
- gen_read_xer(ctx, cpu_gpr[gprn]);
+ TCGv dst = cpu_gpr[gprn];
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ tcg_gen_mov_tl(dst, cpu_xer);
+ tcg_gen_shli_tl(t0, cpu_so, XER_SO);
+ tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
+ tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
+ tcg_gen_or_tl(t0, t0, t1);
+ tcg_gen_or_tl(dst, dst, t2);
+ tcg_gen_or_tl(dst, dst, t0);
+ if (is_isa300(ctx)) {
+ tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
+ tcg_gen_or_tl(dst, dst, t0);
+ tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
+ tcg_gen_or_tl(dst, dst, t0);
+ }
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
}
static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
{
- gen_write_xer(cpu_gpr[gprn]);
+ TCGv src = cpu_gpr[gprn];
+ /* Write all flags, while reading back check for isa300 */
+ tcg_gen_andi_tl(cpu_xer, src,
+ ~((1u << XER_SO) |
+ (1u << XER_OV) | (1u << XER_OV32) |
+ (1u << XER_CA) | (1u << XER_CA32)));
+ tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1);
+ tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1);
+ tcg_gen_extract_tl(cpu_so, src, XER_SO, 1);
+ tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1);
+ tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1);
}
/* LR */
--
2.17.1